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| body fat scale flash mcu HT45F75 revision: v1.10 date: de ? e ?? e ? 1 ?? ? 01 ? de ? e ?? e ? 1 ?? ? 01 ?
rev. 1.10 ? de ? e ?? e ? 1 ?? ? 01 ? rev. 1.10 3 de?e??e? 1?? ?01? HT45F75 body fat scale flash mcu HT45F75 body fat scale flash mcu tale o cotets feates cpu featu ? es .............................................................................................................................. ? pe ? iphe ? al featu ? es ...................................................................................................................... ? gene?al des??iption ............................................................................................. 7 blo?k diag?a? ...................................................................................................... 8 pin assign?ent ........... ......................................................................................... 8 pin des??iption .......... .......................................................................................... 9 a?solute maxi?u? ratings .............................................................................. 11 d.c. cha?a?te?isti?s ........................................................................................... 1? a.c. cha?a?te?isti?s ........................................................................................... 1? ldo+pga+adc+vcm ele?t?i?al cha?a?te?isti?s .......... ................................. 15 effe ? tive nu ?? e ? of bits (enob) ............................................................................................... 17 operational amplifer electrical characteristics (body fat circuit) clo ? king and pipelining .............................................................................................................. 18 p ? og ? a ? counte ? ........................................................................................................................ 19 sta ? k .......................................................................................................................................... ? 0 a ? ith ? eti ? and logi ? unit C alu ............................................................................................... ? 0 flash p?og?a? me?o?y .................................................................................... ?1 st ? u ? tu ? e .................................................................................................................................... ? 1 spe ? ial ve ? to ? s .......................................................................................................................... ? 1 look-up ta ? le ............. ............................................................................................................... ? 1 ta ? le p ? og ? a ? exa ? ple ............................................................................................................. ?? in ci ?? uit p ? og ? a ?? ing C icp .................................................................................................... ? 3 on chip de ? ug suppo ? t C ocds .............................................................................................. ? 3 in appli ? ation p ? og ? a ?? ing C iap ............................................................................................. ?? ram data me?o?y ............................................................................................. 31 st ? u ? tu ? e .................................................................................................................................... 31 gene ? al pu ? pose data me ? o ? y ................................................................................................. 3 ? spe ? ial pu ? pose data me ? o ? y .................................................................................................. 3 ? spe?ial fun?tion registe? des??iption ............................................................ 3? indi ? e ? t add ? essing registe ? s C iar0 ? iar1 ? iar ? .................................................................... 3 ? me ? o ? y pointe ? s C mp0 ? mp1l ? mp1h ? mp ? l ? mp ? h .............................................................. 3 ? a ?? u ? ulato ? C acc ................................................................................................................... 35 p ? og ? a ? counte ? low registe ? C pcl ...................................................................................... 3 ? look-up ta ? le registe ? s C tblp ? tbhp ? tblh ......................................................................... 3 ? status registe ? C status ........................................................................................................ 3 ? rev. 1.10 ? de?e??e? 1?? ?01? rev. 1.10 3 de ? e ?? e ? 1 ?? ? 01 ? HT45F75 body fat scale flash mcu HT45F75 body fat scale flash mcu m ata eoy eeprom data me ? o ? y st ? u ? tu ? e ............................................................................................. 38 eeprom registe ? s ............ ....................................................................................................... 38 reading data f ? o ? the eeprom .............................................................................................. ? 0 w ? iting data to the eeprom ..................................................................................................... ? 0 w ? ite p ? ote ? tion .......................................................................................................................... ? 0 eeprom inte ?? upt ............. ........................................................................................................ ? 0 p ? og ? a ?? ing conside ? ations ............. ........................................................................................ ? 1 os?illato?s .......... ................................................................................................ ?? os ? illato ? ove ? view ............. ...................................................................................................... ?? system clock confgurations ..................................................................................................... ?? exte ? nal c ? ystal/ce ? a ? i ? os ? illato ? C hxt ............................................................................... ? 3 inte ? nal rc os ? illato ? C hirc ............. ....................................................................................... ?? inte ? nal 3 ? khz os ? illato ? C lirc ............................................................................................... ?? exte ? nal 3 ? .7 ? 8khz c ? ystal os ? illato ? C lxt ............. ............................................................... ?? supple ? enta ? y os ? illato ? s ........................................................................................................ ?? ope?ating modes and syste? clo?ks ............................................................. ?? syste ? clo ? ks ........................................................................................................................... ?? syste ? ope ? ation modes .......................................................................................................... ? 8 cont ? ol registe ? ......................................................................................................................... ? 9 fast wake-up ............................................................................................................................. 51 ope ? ating mode swit ? hing ........................................................................................................ 51 stand ? y cu ?? ent conside ? ations ............................................................................................... 5 ? wake-up .................................................................................................................................... 5 ? p ? og ? a ?? ing conside ? ations ............. ....................................................................................... 57 wat?hdog ti?e? ........... ...................................................................................... 57 wat ? hdog ti ? e ? clo ? k sou ?? e ................................................................................................... 57 wat ? hdog ti ? e ? cont ? ol registe ? ............. ................................................................................. 57 wat ? hdog ti ? e ? ope ? ation ........................................................................................................ 59 reset and initialisation ..................................................................................... ?0 reset fun ? tions ............. ............................................................................................................ ? 0 reset initial conditions ............................................................................................................. ? 3 input/output po?ts ............................................................................................ ?? pull-high resisto ? s ..................................................................................................................... ?? po ? t a wake-up ............. ............................................................................................................. ? 7 i/o po ? t cont ? ol registe ? s .......................................................................................................... ? 8 i/o po ? t sou ?? e cu ?? ent cont ? ol ................................................................................................. ? 9 i/o pin st ? u ? tu ? es ....................................................................................................................... 70 p ? og ? a ?? ing conside ? ations ............. ........................................................................................ 70 ti?e? modules C tm .......... ................................................................................ 71 int ? odu ? tion ................................................................................................................................ 71 tm ope ? ation ............. ................................................................................................................ 71 tm clo ? k sou ?? e ............. ........................................................................................................... 71 rev. 1.10 ? de ? e ?? e ? 1 ?? ? 01 ? rev. 1.10 5 de?e??e? 1?? ?01? HT45F75 body fat scale flash mcu HT45F75 body fat scale flash mcu tm inte ?? upts .............................................................................................................................. 7 ? tm exte ? nal pins ....................................................................................................................... 7 ? tm input/output pin cont ? ol registe ? s ............. ......................................................................... 7 ? p ? og ? a ?? ing conside ? ations ............. ........................................................................................ 73 co?pa?t type tm C ctm .................................................................................. 7? co ? pa ? t tm ope ? ation ............................................................................................................. 7 ? co ? pa ? t type tm registe ? des ?? iption ..................................................................................... 75 co ? pa ? t type tm ope ? ating modes ........................................................................................ 79 pe?iodi? type tm C ptm .................................................................................... 85 pe ? iodi ? tm ope ? ation ............. .................................................................................................. 85 pe ? iodi ? type tm registe ? des ?? iption ...................................................................................... 8 ? pe ? iodi ? type tm ope ? ating modes ........................................................................................... 90 inte?nal powe? supply ...................................................................................... 99 analog to digital conve?te? C adc ........... ...................................................... 101 a/d ove ? view ............. .............................................................................................................. 101 a/d data rate defnition .......................................................................................................... 10 ? a/d conve ? te ? registe ? des ?? iption ......................................................................................... 10 ? programmable gain amplifer C pga ....................................................................................... 10 ? a/d conve ? te ? data registe ? s C adrl ? adrm ? adrh ............................................................ 10 ? a/d conve ? te ? cont ? ol registe ? s C adcr0 ? adcr1 ? adcs .................................................... 105 a/d ope ? ation .......................................................................................................................... 107 su ?? a ? y of a/d conve ? sion steps ............. ............................................................................. 108 p ? og ? a ?? ing conside ? ations ............. ...................................................................................... 108 a/d t ? ansfe ? fun ? tion ............. ................................................................................................. 109 a/d conve ? ted data ................................................................................................................. 110 a/d conve ? ted data to voltage ............. .................................................................................... 110 a/d p ? og ? a ?? ing exa ? ple ...................................................................................................... 111 te?pe?atu?e senso? ........................................................................................ 11? se?ial inte?fa?e module C sim ......................................................................... 11? spi inte ? fa ? e ........................................................................................................................... 11 ? i ? c inte ? fa ? e ............ ................................................................................................................. 119 uart module se?ial inte?fa?e with ir ca??ie? ............................................... 1?9 uart module featu ? es ............................................................................................................ 1 ? 9 uart module ove ? view ........................................................................................................... 1 ? 9 uart exte ? nal pin inte ? fa ? ing .................................................................................................. 1 ? 9 uart data t ? ansfe ? s ? he ? e ..................................................................................................... 1 ? 9 uart status and ? ont ? ol ? egiste ? s ........................................................................................... 130 baud rate gene ? ato ? ............................................................................................................... 135 uart setup and cont ? ol .......................................................................................................... 137 uart t ? ans ? itte ? ...................................................................................................................... 138 uart ? e ? eive ? .......................................................................................................................... 139 managing ? e ? eive ? e ?? o ? s ......................................................................................................... 1 ? 0 uart module inte ?? upt st ? u ? tu ? e ............................................................................................. 1 ? 1 rev. 1.10 ? de?e??e? 1?? ?01? rev. 1.10 5 de ? e ?? e ? 1 ?? ? 01 ? HT45F75 body fat scale flash mcu HT45F75 body fat scale flash mcu uart module powe ? down and wake-up ............. .................................................................. 1 ? 3 inte??upts .......................................................................................................... 1?5 inte ?? upt registe ? s .................................................................................................................... 1 ? 5 inte ?? upt ope ? ation ................................................................................................................... 151 exte ? nal inte ?? upt ............. ......................................................................................................... 153 a/d conve ? te ? inte ?? upt ............................................................................................................ 153 multi-fun ? tion inte ?? upt ............................................................................................................. 153 se ? ial inte ? fa ? e module inte ?? upt .............................................................................................. 15 ? ti ? e base inte ?? upts ................................................................................................................ 15 ? i ? c ti ? e out inte ?? upt ............ .................................................................................................. 155 uart inte ?? upt ............. ............................................................................................................ 15 ? eeprom inte ?? upt ............. ...................................................................................................... 15 ? lvd inte ?? upt ............................................................................................................................ 15 ? tm inte ?? upts ............................................................................................................................ 157 inte ?? upt wake-up fun ? tion ...................................................................................................... 157 p ? og ? a ?? ing conside ? ations ............. ...................................................................................... 157 low voltage dete?to? C lvd .......... ................................................................. 158 lvd registe ? ............. ............................................................................................................... 158 lvd ope ? ation .......................................................................................................................... 159 body fat measu?e?ent fun?tion ................................................................... 1?0 sine wave gene ? ato ? ............................................................................................................... 1 ? 0 amplifer ............. ...................................................................................................................... 1 ?? filte ? ......................................................................................................................................... 1 ?? &rqjxudwlrq?swlrqv ..................................................................................... 1?5 appli?ation ci??uits ........... .............................................................................. 1?5 inst?u?tion set .................................................................................................. 1?? int ? odu ? tion .............................................................................................................................. 1 ?? inst ? u ? tion ti ? ing ..................................................................................................................... 1 ?? moving and t ? ansfe ?? ing data .................................................................................................. 1 ?? a ? ith ? eti ? ope ? ations ............................................................................................................... 1 ?? logi ? al and rotate ope ? ation .................................................................................................. 1 ? 7 b ? an ? hes and cont ? ol t ? ansfe ? ................................................................................................ 1 ? 7 bit ope ? ations .......................................................................................................................... 1 ? 7 ta ? le read ope ? ations ............................................................................................................ 1 ? 7 othe ? ope ? ations ............. ......................................................................................................... 1 ? 7 inst?u?tion set su??a?y .......... ...................................................................... 1?8 ta ? le conventions .................................................................................................................... 1 ? 8 extended inst ? u ? tion set ............. ............................................................................................. 170 ?qvwuxfwlrq'hqlwlrq ....................................................................................... 17? extended instruction defnition ................................................................................................ 181 pa?kage info??ation ....................................................................................... 188 ? 8-pin lqfp (7 ?? 7 ?? ) outline di ? ensions ....................................................................... 189 rev. 1.10 ? de ? e ?? e ? 1 ?? ? 01 ? rev. 1.10 7 de?e??e? 1?? ?01? HT45F75 body fat scale flash mcu HT45F75 body fat scale flash mcu feates cu feates ? operating v oltage: f sys =8mhz: 2.2v~5.5v f sys =12mhz: 2.7v~5.5v f sys =20mhz: 4.5v~5.5v ? up to 0.2s instruction cycle with 20mhz system clock at v dd =5v ? power down and wake-up functions to reduce power consumption ? four oscillators: external crystal hxt external 32.768khz crystal lxt internal high speed rc hirc internal low speed 32 khz rc lirc ? multi-mode operation: normal, slow, idle and sleep ? fully integrated internal 4.8mhz, 4.82mhz and 4.83mhz oscillator requires no external components ? all instructions executed in 1~3 instruction cycles ? table read instructions ? 115 powerful instructions ? 8-level subroutine nesting ? bit manipulation instruction ? fla sh program memory: 4k16 ? ram data memory: 2568 ? true eeprom memory: 648 ? in application programming function iap ? watchdog t imer function ? 27 bidirectional i/o lines ? dual pin-shared external interrupts ? multiple t imer modules for time measure, input capture, compare matc h output, pwm output or single pulse output function ? dual t ime-base functions for generation of fxed time interrupt signals ? 2 differential channels 20-bit resolution delta-sigma a/d converter ? low voltage reset function ? low voltage detect function ? internal ldo with bypass function for pga, adc or external sensor power supply ? serial interfaces module -- sim for spi or i 2 c ? uart with ir carrier ? body fat circuit ? flash program memory can be re-programmed up to 100,000 times ? flash program memory data retention > 10 years ? true eeprom data memory can be re-programmed up to 1,000,000 times ? true eeprom data memory data retention > 10 years ? package type: 48-pin lqfp rev. 1.10 ? de?e??e? 1?? ?01? rev. 1.10 7 de ? e ?? e ? 1 ?? ? 01 ? HT45F75 body fat scale flash mcu HT45F75 body fat scale flash mcu eeal escto this holtek device is specifically designed for body fat scale applications. measuring body fat uses a t echnique where by a n ac c urrent fl owing t hrough t he hum an body i s m easured a nd t hen used to calculate a body fat value. the specialis ed circuits to do this are a weight measurement circuit and a fat measurement circu it. the weight measurement circuit uses an external load cell to output a signal, which after amplifcation by an op a, and then conversion using an adc, reads the corresponding value as the calculated weight. the fat measurement circuit uses an ac signal via an electrode slice to fow through human body . after amplifcation by an internal op a, and then conversion by an adc, the measured value is one representing body impedance, which is used to calculate the corresponding body fat value. the device, which integrates the body fat scale circuitry , is a flash memory a/d type 8-bit high performance risc architecture microcontroller which includes a multi-channel 20-bit delta-sigma a/d (?a/d) converter , which is designed for applications that interface directly to analog signals and wh ich r equire a l ow n oise a nd h igh a ccuracy a nalog t o d igital c onverter. of fering u sers t he convenience of flash memory multi-programming features, this device also includes a wide range of functio ns and features. other memory includes an area of ram data memory as well as an area of true eeprom memory for storage of non-volatile data such as serial numbers, calibration data etc. analog features include a multi-cha nnel 20-bit ?a/d converter and programmable gain amplifer (pga) functions. an extremely fexible t imer module provides timing , pulse generation and pwm generation functions. in addition, an internal ldo function provides various power options to the internal and external devices. protective features such as an internal w atchdog t imer, low v oltage reset and low v oltage detector coupled with excellent noise immunity and esd protection ensure that reliable operation is maintained in hostile electrical environments. a ful l c hoice of va rious i nternal a nd e xternal osc illator func tions i s provi ded i ncluding a ful ly integrated system oscillator which requires no external components for its implementation. the ability t o opera te a nd swi tch dyna mically be tween a ra nge of opera ting m odes usi ng di fferent clock sources gives users the ability to optimise microcontroller operation and minimise power consumption. rev. 1.10 8 de ? e ?? e ? 1 ?? ? 01 ? rev. 1.10 9 de?e??e? 1?? ?01? HT45F75 body fat scale flash mcu HT45F75 body fat scale flash mcu bloc aa flash / eeprom p?og?a??ing ci??uit?y 8-?it risc mcu co?e ldo + op + ?0-?it a/d conve?te? low voltage dete?t wat?hdog ti?e? low voltage reset inte?nal hirc/lirc os?illato?s i?pedan?e measu?e?ent inte??upt cont?olle? exte?nal hxt/lxt os?illato?s reset ci??uit eeprom data me?o?y flash p?og?a? me?o?y iap ram data me?o?y ti?e bases i/o sim ti?e? modules uart pin assign?ent ht?5f75/ht?5v75 ?8 lqfp-a 1 ? 3 ? 5 ? 7 8 9 10 11 1? 13 1? 15 1? 17 18 19 ?0 ?1 ?? ?3 ?? ?5 ?? ?7 ?8 ?9 30 31 3? 33 3? 35 3? ?5 ???7?8 373839?0?1???3?? vout/avdd avss vdd pb?/osc? pb1/osc1 vss pb0 pa5/lvdin pd1 pd? pb3/xt1 pb?/xt? pa?/icpck/ocdsck pa0/icpda/ocdsda pa1/tx pc?/tck0 pa?/int0 pc3/tp0_0 pa?/sck/scl pd0/int1 pa3/rx pc1/scs pa7/sdi/sda pc0/sdo to cp0n rfc an0 an1 vrefp vrefn vcm an? an3 fvr fir sin fvl fil rf? rf1 pb5/tp?_1 pb?/tp?_0 pc7/tp1_1 pc?/tp1_0 pb7/tck? pc?/tp0_1 pc5/tck1 note: 1. if the pin-shared pin functions have multiple outputs simultaneously , its pin names at the right side of the / sign can be used for higher priority. 2. the ocdsda and ocdsck pins are the ocds dedicated pins and only available for the ht45v75 device which is the ocds ev chip for the HT45F75 device. rev. 1.10 8 de?e??e? 1?? ?01? rev. 1.10 9 de ? e ?? e ? 1 ?? ? 01 ? HT45F75 body fat scale flash mcu HT45F75 body fat scale flash mcu escto the function of each pin is listed in the following table, however the details behind how each pin is confgured is contained in other sections of the datasheet. pa0/icpda/ ocdsda pa0 papu pawu st cmos gene ? al pu ? pose i/o. registe ? ena ? led pull-up and wake-up. icpda st cmos icp add ? ess/data ocdsda st cmos ocds add ? ess/data - fo ? ev ? hip only. pa1/tx pa1 papu pawu st cmos gene ? al pu ? pose i/o. registe ? ena ? led pull-up and wake-up. tx ucr1 ucr ? cmos uart t ? ans ? eive ? pin pa ? /icpck/ ocdsck pa ? papu pawu st cmos gene ? al pu ? pose i/o. registe ? ena ? led pull-up and wake-up. icpck st icp ? lo ? k ocdsck st ocds ? lo ? k - fo ? ev ? hip only. pa3/rx pa3 papu pawu st cmos gene ? al pu ? pose i/o. registe ? ena ? led pull-up and wake-up. rx ucr1 ucr ? st uart ? e ? eive ? pin pa ? /int0 pa ? papu pawu st cmos gene ? al pu ? pose i/o. registe ? ena ? led pull-up and wake-up. int0 intc0 st exte ? nal inte ?? upt 0 input pa5/lvdin pa5 papu pawu st cmos gene ? al pu ? pose i/o. registe ? ena ? led pull-up and wake-up. lvdin lvdc st lvd input pa ? /sck/scl pa ? papu pawu st cmos gene ? al pu ? pose i/o. registe ? ena ? led pull-up and wake-up. sck simc0 st cmos spi se ? ial ? lo ? k scl simc0 st cmos i ? c ? lo ? k line pa7/sdi/sda pa7 papu pawu st cmos gene ? al pu ? pose i/o. registe ? ena ? led pull-up and wake-up. sdi simc0 st spi se ? ial data input sda simc0 st cmos i ? c data line pb0 pb0 pbpu st cmos gene ? al pu ? pose i/o. registe ? ena ? led pull-up. pb1/osc1 pb1 pbpu st cmos gene ? al pu ? pose i/o. registe ? ena ? led pull-up. osc1 co hxt hxt os ? illato ? input pb ? /osc ? pb ? pbpu st cmos gene ? al pu ? pose i/o. registe ? ena ? led pull-up. osc ? co hxt hxt os ? illato ? output pb3/xt1 pb3 pbpu st cmos gene ? al pu ? pose i/o. registe ? ena ? led pull-up. xt1 co lxt lxt os ? illato ? input pb ? /xt ? pb ? pbpu st cmos gene ? al pu ? pose i/o. registe ? ena ? led pull-up. xt ? co lxt lxt os ? illato ? output rev. 1.10 10 de ? e ?? e ? 1 ?? ? 01 ? rev. 1.10 11 de?e??e? 1?? ?01? HT45F75 body fat scale flash mcu HT45F75 body fat scale flash mcu ae fcto t t t esctos pb5/tp ? _1 pb5 pbpu st cmos gene ? al pu ? pose i/o. registe ? ena ? led pull-up. tp ? _1 ctrl0 ptm ? c0 st cmos tm ? input/output pb ? /tp ? _0 pb ? pbpu st cmos gene ? al pu ? pose i/o. registe ? ena ? led pull-up. tp ? _0 ctrl0 ptm ? c0 st cmos tm ? input/output pb7/tck ? pb7 pbpu st cmos gene ? al pu ? pose i/o. registe ? ena ? led pull-up. tck ? ptm ? c0 st tm ? ? lo ? k input pc0/sdo pc0 pcpu st cmos gene ? al pu ? pose i/o. registe ? ena ? led pull-up. sdo simc0 cmos spi se ? ial data output pc1/scs pc1 pcpu st cmos gene ? al pu ? pose i/o. registe ? ena ? led pull-up. scs simc0 st cmos spi slave sele ? t pin pc ? /tck0 pc ? pcpu st cmos gene ? al pu ? pose i/o. registe ? ena ? led pull-up. tck0 tm0c0 st tm0 ? lo ? k input pc3/tp0_0 pc3 pcpu st cmos gene ? al pu ? pose i/o. registe ? ena ? led pull-up. tp0_0 ctrl0 tm0c0 st cmos tm0 input/output pc ? /tp0_1 pc ? pcpu st cmos gene ? al pu ? pose i/o. registe ? ena ? led pull-up. tp0_1 ctrl0 tm0c0 st cmos tm0 input/output pc5/tck1 pc5 pcpu st cmos gene ? al pu ? pose i/o. registe ? ena ? led pull-up. tck1 ptm1c0 st tm1 ? lo ? k input pc ? /tp1_0 pc ? pcpu st cmos gene ? al pu ? pose i/o. registe ? ena ? led pull-up. tp1_0 ctrl0 ptm1c0 st cmos tm1 input/output pc7/tp1_1 pc7 pcpu st cmos gene ? al pu ? pose i/o. registe ? ena ? led pull-up. tp1_1 ctrl0 ptm1c0 st cmos tm1 input/output pd0/int1 pd0 pdpu st cmos gene ? al pu ? pose i/o. registe ? ena ? led pull-up. int1 intc0 st exte ? nal inte ?? upt 1 input pd1~pd ? pdn pdpu st cmos gene ? al pu ? pose i/o. registe ? ena ? led pull-up. sin sin ao sine wave output fvl fvl ai ao left foot channel 1 fil fil ai ao left foot channel ? rf1 rf1 ai ao refe ? en ? e 1 i ? pedan ? e channel rf ? rf ? ai ao refe ? en ? e ? i ? pedan ? e channel fir fir ai ao right foot channel ? fvr fvr ai ao right foot channel 1 to to ao opa output rev. 1.10 10 de?e??e? 1?? ?01? rev. 1.10 11 de ? e ?? e ? 1 ?? ? 01 ? HT45F75 body fat scale flash mcu HT45F75 body fat scale flash mcu ae fcto t t t esctos cp0n cp0n ai peak dete ? to ? input rfc rfc ai adc analog input vout/avdd vout pwr ldo output pin avdd pwr analog powe ? supply avss avss pwr analog g ? ound vcm vcm pwr adc inte ? nal co ?? on mode voltage output verfp verfp pwr adc positive refe ? en ? e input (exte ? nal) verfn verfn pwr adc negative refe ? en ? e input (exte ? nal) an0~an3 ann ai adc input channel 0~3 vdd vdd pwr digital powe ? supply vss vss pwr digital g ? ound note: i/t: input type; o/t: output type; otp: optional by confguration option (co) or register option; pwr: power; co: confguration option; st: schmitt t rigger input; cmos: cmos output; ai: analog input; ao: analog output; hxt: high frequency crystal oscillator; lxt: low frequency crystal oscillator. supply v oltage .............. .................................................................................... v ss -0.3v to v ss +6.0v input v oltage .............. ........................................................................................ v ss -0.3v to v dd +0.3v storage t emperature ............... ...................................................................................... -50c to 1 25c operating t emperature .............. ...................................................................................... -40c to 85c i ol t otal .............. ................................................................................................... ..................... 150ma i oh t otal .............. ....................................................................................................................... -100ma total power dissipation .............. .............................................................................................. 500mw note: thes e are s tress ratings only . s tresses exceeding the range s pecified under a bsolute maximum rating s may cause substantial damage to the device. functional operation of this device at other conditions beyond those listed in the specifcation is not implied and prolonged exposure to extreme conditions may affect device reliability. rev. 1.10 1 ? de ? e ?? e ? 1 ?? ? 01 ? rev. 1.10 13 de?e??e? 1?? ?01? HT45F75 body fat scale flash mcu HT45F75 body fat scale flash mcu c chaactestcs ta= ? 5c sy??ol pa?a?ete? test conditions min. typ. max. unit v dd conditions v dd1 ope ? ating voltage (hxt) f sys =8mhz ? . ? 5.5 v f sys =1 ? mhz ? .7 5.5 v f sys =1 ? mhz ? .5 5.5 v v dd ? ope ? ating voltage (hirc) f sys = ? .8mhz ? . ? 5.5 v i dd1 ope ? ating cu ?? ent (hxt ? f sys =f h ? f s =f sub =f lxt o ? f lirc ) 3v no load ? f h =8mhz ? ldo ? ? ha ? ge pu ? p ? adc off ? wdt ena ? le 1.0 1.5 ? a 5v ? .5 ? ? a 3v no load ? f h =10mhz ? ldo ? ? ha ? ge pu ? p ? adc off ? wdt ena ? le 1. ? ? .0 ? a 5v ? .8 ? .5 ? a 3v no load ? f h =1 ? mhz ? ldo ? ? ha ? ge pu ? p ? adc off ? wdt ena ? le 1.5 ? .5 ? a 5v 3.5 5.5 ? a 5v no load ? f h =1 ? mhz ? ldo ? ? ha ? ge pu ? p ? adc off ? wdt ena ? le ? .5 7.0 ? a 5v no load ? f h = ? 0mhz ? ldo ? ? ha ? ge pu ? p ? adc off ? wdt ena ? le 5.5 8.5 ? a i dd ? ope ? ating cu ?? ent (hirc ? f sys =f h ? f s =f sub =f lxt o ? f lirc ) 3v no load ? f h = ? .8mhz ? ldo ? ? ha ? ge pu ? p ? adc off ? wdt ena ? le 0.7 1. ? ? a 5v 1.5 ? .5 ? a 3v no load ? f h = ? .8 ? mhz ? ldo ? ? ha ? ge pu ? p ? adc off ? wdt ena ? le 1. ? ? .0 ? a 5v ? .8 ? .5 ? a 3v no load ? f h = ? .83mhz ? ldo ? ? ha ? ge pu ? p ? adc off ? wdt ena ? le 1.8 3.0 ? a 5v ? .0 ? .0 ? a i dd3 ope ? ating cu ?? ent (hxt ? f sys =f l ? f s =f sub =f lxt o ? f lirc ) 3v no load ? f h =1 ? mhz ? f l =f h / ?? adc off ? wdt ena ? le 0.9 1.5 ? a 5v ? .1 3.3 ? a 3v no load ? f h =1 ? mhz ? f l =f h / ?? ldo ? ? ha ? ge pu ? p ? adc off ? wdt ena ? le 0. ? 1.0 ? a 5v 1. ? ? .5 ? a 3v no load ? f h =1 ? mhz ? f l =f h /8 ? ldo ? ? ha ? ge pu ? p ? adc off ? wdt ena ? le 0. ? 8 0.8 ? a 5v 1. ? ? .0 ? a 3v no load ? f h =1 ? mhz ? f l =f h /1 ?? ldo ? ? ha ? ge pu ? p ? adc off ? wdt ena ? le 0. ?? 0.7 ? a 5v 1.1 1.7 ? a 3v no load ? f h =1 ? mhz ? f l =f h /3 ?? ldo ? ? ha ? ge pu ? p ? adc off ? wdt ena ? le 0.38 0. ? ? a 5v 1.0 1.5 ? a 3v no load ? f h =1 ? mhz ? f l =f h / ??? ldo ? ? ha ? ge pu ? p ? adc off ? wdt ena ? le 0.3 ? 0.55 ? a 5v 1.0 1.5 ? a i dd ? ope ? ating cu ?? ent (lxt ? f sys = f sub =f lxt ? f s =f sub =f lxt ) 3v no load ? ldo ? ? ha ? ge pu ? p ? adc off ? wdt ena ? le ? lxtlp=0 10 ? 0 a 5v 30 50 a 3v no load ? ldo ? ? ha ? ge pu ? p ? adc off ? wdt ena ? le ? lxtlp =1 10 ? 0 a 5v 30 50 a i dd5 ope ? ating cu ?? ent (lirc ? f sys = f sub =f lirc ? f s =f sub =f lirc ) 3v no load ? ldo ? ? ha ? ge pu ? p ? adc off ? wdt ena ? le 10 ? 0 a 5v 30 50 a i stb1 stand ? y cu ?? ent (idle) (hxt ? f sys =f h ? f s =f sub =f lxt o ? f lirc ) 3v no load ? syste ? halt ? ldo ? ? ha ? ge pu ? p ? adc off ? wdt ena ? le ? f sys =1 ? mhz 0. ? 1.0 ? a 5v 1. ? ? .0 ? a i stb ? stand ? y cu ?? ent (idle) (hxt ? f sys =off ? f s =t1) 3v no load ? syste ? halt ? ldo ? ? ha ? ge pu ? p ? adc off ? wdt ena ? le ? f sys =1 ? mhz 1.3 3.0 a 5v ? . ? 5.0 a rev. 1.10 1? de?e??e? 1?? ?01? rev. 1.10 13 de ? e ?? e ? 1 ?? ? 01 ? HT45F75 body fat scale flash mcu HT45F75 body fat scale flash mcu syol aaete test codtos m ty ma ut codtos i stb3 stand ? y cu ?? ent (idle) (hxt ? f sys =off ? f s =f sub =f lxt o ? f lirc ) 3v no load ? syste ? halt ? ldo ? ? ha ? ge pu ? p ? adc off ? wdt ena ? le ? f sys =1 ? mhz 1.3 3.0 a 5v ? . ? 5.0 a i stb ? stand ? y cu ?? ent (idle) (hirc ? f sys =off ? f s =f sub =f lirc ) 3v no load ? syste ? halt ? ldo ? ? ha ? ge pu ? p ? adc off ? wdt ena ? le ? f sys = ? .83mhz 1.3 3.0 a 5v ? . ? 5.0 a i stb5 stand ? y cu ?? ent (idle) (hxt ? f sys =f l ? f s =f sub =f lxt o ? f lirc ) 3v no load ? syste ? halt ? ldo ? ? ha ? ge pu ? p ? adc off ? wdt ena ? le ? f sys =1 ? mhz/ ?? 0.3 ? 0. ? ? a 5v 0.85 1. ? ? a i stb ? stand ? y cu ?? ent (idle) (hxt ? f sys =off ? f s =f sub =f lxt o ? f lirc ) 3v no load ? syste ? halt ? ldo ? ? ha ? ge pu ? p ? adc off ? wdt ena ? le ? f sys =1 ? mhz/ ?? 1.3 3.0 a 5v ? . ? 5.0 a i stb7 stand ? y cu ?? ent (idle) (lxt ? f sys = f sub =f lxt ? f s =f sub =f lxt ) 3v no load ? syste ? halt ? ldo ? ? ha ? ge pu ? p ? adc off ? wdt ena ? le ? f sys =3 ? 7 ? 8hz 1.9 ? .0 a 5v 3.3 7.0 a i stb8 stand ? y cu ?? ent (idle) (lxt ? f sys =off ? f s =t1) 3v no load ? syste ? halt ? ldo ? ? ha ? ge pu ? p ? adc off ? wdt ena ? le ? f sys =3 ? 7 ? 8hz 1.3 3.0 a 5v ? . ? 5.0 a i stb9 stand ? y cu ?? ent (idle) (lxt ? f sys =off ? f s =f sub =f lxt ) 3v no load ? syste ? halt ? ldo ? ? ha ? ge pu ? p ? adc off ? wdt ena ? le ? f sys =3 ? 7 ? 8hz 1.3 3.0 a 5v ? .. ? 5.0 a i stb10 stand ? y cu ?? ent (idle) (lirc ? f sys =off ? f s =f sub =f lirc ) 3v no load ? syste ? halt ? ldo ? ? ha ? ge pu ? p ? adc off ? wdt ena ? le ? f sys =3 ? khz 1.3 3.0 a 5v ? . ? 5.0 a i stb11 stand ? y cu ?? ent (sleep) (hxt ? f sys =off ? f s =f sub =f lxt o ? f lirc ) 3v no load ? syste ? halt ? ldo ? ? ha ? ge pu ? p ? adc off ? wdt disa ? le ? f sys =1 ? mhz 0.1 1 a 5v 0.3 ? a i stb1 ? stand ? y cu ?? ent (sleep) (hxt ? f sys =off ? f s =f sub =f lxt ) 3v no load ? syste ? halt ? ldo ? ? ha ? ge pu ? p ? adc off ? wdt ena ? le ? f sys =1 ? mhz 1.3 5 a 5v ? . ? 10 a i stb13 stand ? y cu ?? ent (sleep) (hxt ? f sys =off ? f s =f sub =f lirc ) 3v no load ? syste ? halt ? ldo ? ? ha ? ge pu ? p ? adc off ? wdt ena ? le ? f sys =1 ? mhz 1.3 5 a 5v ? . ? 10 a i stb1 ? stand ? y cu ?? ent (sleep) (lxt ? f sys =off ? f s =f sub =f lxt ) 3v no load ? syste ? halt ? ldo ? ? ha ? ge pu ? p ? adc off ? wdt ena ? le ? f sys =3 ? 7 ? 8hz 1.3 3.0 a 5v ? . ? 5.0 a i stb15 stand ? y cu ?? ent (sleep) (hxt ? f sys =off ? f s =f sub =f lxt o ? f lirc ) no load ? syste ? halt ? ldo ? ? ha ? ge pu ? p ? adc off ? wdt disa ? le ? f sys =1 ? mhz ? lvr ena ? le and lvden=1 90 1 ? 0 a v il input low voltage fo ? i/o po ? ts ? tckn ? tpn_0 ? tpn_1 and intn 0 0. ? v dd v 5v 0 1.5 v v ih input high voltage fo ? i/o po ? ts ? tckn ? tpn_0 ? tpn_1 and intn 0.8v dd v dd v 5v 3.5 5 v v lvr1 low voltage reset voltage lvr ena ? le ? ? .1v option -5% ? .1 +5% v v lvr ? lvr ena ? le ? ? .55v option ? .55 v v lvr3 lvr ena ? le ? 3.15v option 3.15 v v lvr ? lvr ena ? le ? 3.8v option 3.8 v i lvr low voltage reset cu ?? ent lvr ena ? le ? lvden=0 ? 0 90 a v lvd1 low voltage dete ? to ? input pin voltage lvden=1 ? v lvd =1.0 ? v ? vlvd[ ? :0]=000 ? -10% 1.0 ? +10% v rev. 1.10 1 ? de ? e ?? e ? 1 ?? ? 01 ? rev. 1.10 15 de?e??e? 1?? ?01? HT45F75 body fat scale flash mcu HT45F75 body fat scale flash mcu syol aaete test codtos m ty ma ut codtos v lvd ? low voltage dete ? to ? voltage lvden=1 ? v lvd = ? . ? v -5% ? . ? +5% v v lvd3 lvden=1 ? v lvd = ? . ? v ? . ? v v lvd ? lvden=1 ? v lvd = ? .7v ? .7 v v lvd5 lvden=1 ? v lvd =3.0v 3.0 v v lvd ? lvden=1 ? v lvd =3.3v 3.3 v v lvd7 lvden=1 ? v lvd =3. ? v 3. ? v v lvd8 lvden=1 ? v lvd = ? .0v ? .0 v i lvd1 low voltage dete ? to ? cu ?? ent lvr disa ? le ? lvden=1 75 1 ? 0 a i lvd ? lvr ena ? le ? lvden=1 90 150 a i ol sink ? u ?? ent fo ? i/o po ? ts 3v v ol =0.1v dd 18 3 ? ? a 5v v ol =0.1v dd ? 0 80 ? a i oh sou ?? e ? u ?? ent fo ? i/o po ? ts 3v v oh =0.9v dd ? pxps=00 -1.0 - ? .0 ? a 5v v oh =0.9v dd ? pxps=00 - ? .0 - ? .0 ? a 3v v oh =0.9v dd ? pxps=01 -1.75 -3.5 ? a 5v v oh =0.9v dd ? pxps=01 -3.5 -7.0 ? a 3v v oh =0.9v dd ? pxps=10 - ? .5 -5.0 ? a 5v v oh =0.9v dd ? pxps=10 -5.0 -10 ? a 3v v oh =0.9v dd ? pxps=11 -5.5 -11 ? a 5v v oh =0.9v dd ? pxps=11 -11 - ?? ? a r ph pull-high resistan ? e of i/o po ? ts 3v ? 0 ? 0 100 k 5v 10 30 50 k ta= ? 5c sy??ol pa?a?ete? test conditions min. typ. max. unit v dd conditions f sys1 syste ? clo ? k (hxt) ? . ? ~5.5v 0. ? 8 mhz ? .7~5.5v 0. ? 10 mhz 3.3~5.5v 0. ? 1 ? mhz ? .5~5.5v 0. ? 1 ? mhz f sys ? syste ? clo ? k (hirc) 5v ta= ? 5c - ? % ? .8 ? + ? % mhz f sys3 syste ? clo ? k (lxt) 3 ? 7 ? 8 hz f lirc syste ? clo ? k (lirc) 5v ta= ? 5c -10% 3 ? +10% khz ? . ? v~5.5v ta=- ? 0c~85c -50% 3 ? + ? 0% khz t sst syste ? sta ? t-up ti ? e ? pe ? iod (wake-up f ? o ? halt) f sys =hxt o ? lxt 10 ?? t sys f sys =hirc 1 ? f sys =lirc 1~ ? t rstd syste ? reset delay ti ? e (powe ? on reset) ? 5 50 100 ? s syste ? reset delay ti ? e (any reset ex ? ept powe ? on reset) 8.3 1 ? .7 33.3 ? s t int inte ?? upt pulse width 10 s t lvr low voltage width to reset 1 ? 0 ?? 0 ? 80 s t lvd low voltage width to inte ?? upt ? 0 1 ? 0 ?? 0 s rev. 1.10 1? de?e??e? 1?? ?01? rev. 1.10 15 de ? e ?? e ? 1 ?? ? 01 ? HT45F75 body fat scale flash mcu HT45F75 body fat scale flash mcu syol aaete test codtos m ty ma ut codtos t lvds lvdo sta ? le ti ? e fo ? lvr ena ? le ? lvd off on 15 s fo ? lvr disa ? le ? lvd off on 150 s t eerd eeprom read ti ? e ? t sys t eewr eeprom w ? ite ti ? e 1 ? ? ? s t timer tckn and ti ? e ? captu ? e input pulse width 0.3 s ote t sys i sys dopd letral aratert ta= ? 5c sy??ol pa?a?ete? test conditions min. typ. max. unit v dd conditions v in ldo supply voltage ? .7 5.5 v i voreg ldo ope ? ating ? u ?? ent no load ? ldovs[1:0]=00 ? ? 00 5 ? 0 a v oreg ldo output voltage (i l =0.1 ? a ? v in >v oreg +0. ? v ) ldovs[1:0]=00 ? -5% ? . ? +5% v ldovs[1:0]=01 ? ? . ? ldovs[1:0]=10 ? ? .9 ldovs[1:0]=11 ? 3.3 d ? opout voltage (i l =10 ? a) ldovs[1:0]=00 ? 100 ? v ldovs[1:0]=01 ? 130 ldovs[1:0]=10 ? 180 ldovs[1:0]=11 ? ? 00 te ? pe ? atu ? e d ? ift ldovs[1:0]= 00 ? i l =100a ta=- ? 0 c~85c ? 00 pp ? / c v oreg voltage d ? ift ? . 7v~5.5v -0.3 +0.3 %/v v load load regulation ? .7v load=0 ? a~10 ? a ? mcu halt ? ldo= ? . ? v ? ldo ena ? le ? o the ? fun ? tion disa ? le ? 5 50 ? v v cm vcm output voltage vcms=0 ? av dd =3.3v ? no load -5% 1.05 +5% v vcms=1 ? av dd =3.3v ? no load -5% 1. ? 5 +5% v i l= 200a 0.98 1.0 ? v te ? pe ? atu ? e d ? ift i l= 10a, ta=- ? 0 c~85c ? 00 pp ? / c av dd voltage d ? ift no load ? av dd = ? . ? v~3.3v 100 v/v t vcm vcm tu ? n on sta ? le ti ? e 10 ? s i cmsrc vcm sou ?? e ? u ?? ent v cm d ? op ? % of v cm 1 ? a i cmsnk vcm sink ? u ?? ent v cm ? aise ? % of v cm 1 ? a rev. 1.10 1 ? de ? e ?? e ? 1 ?? ? 01 ? rev. 1.10 17 de?e??e? 1?? ?01? HT45F75 body fat scale flash mcu HT45F75 body fat scale flash mcu syol aaete test codtos m ty ma ut codtos adc & adc internal reference voltage (delta sigma adc) av dd supply voltage fo ? vcm ? adc ? pga ? . ? 3.3 v i cm +i pgia +i adc ope ? ating ? u ?? ent fo ? vcm ? pga and adc vcm ena ? le ? vrbufp=1 and vrbufn=1 900 vcm ena ? le ? vrbufp=0 and vrbufn=0 ? 00 750 vcm disa ? le ? vrbufp=0 and vrbufn=0 500 ? 50 i adstb stand ? y ? u ?? ent syste ? halt ? no load 1 rs ad adc ? esolution ? 0 bit nnfc noise f ? ee code pga gain=1 ? 8 data rate=1 0hz 15. ? bit enob effe ? tive nu ?? e ? of ? its pga gain=1 ? 8 data rate=1 0hz 18.1 bit f ad a/d clo ? k f ? equen ? y ( f mclk ) ? .8 mhz f ado adc output data rate f mclk = ? .8mhz flms[ ? :0]=000 ? adc clk=f mclk /30 5 ?? 5 hz f mclk = ? .8mhz flms[ ? :0]=010 ? adc clk=f mclk /1 ? 1 ? 15 ? 3 v ref+ refe ? en ? e input voltage vrefs=1 ? vrbufp=0 and vrbufn=0 0.9 ? 1. ? 5 ? . ? v v ref- 0 0 1.0 v ref v ref =(v ref+ ) - (v ref- ) 0.9 ? 1. ? 5 1. ?? pga v di+ ? v di- a ? solute/ ? o ?? on input voltage 0. ? av dd -1.1 v '? diffe ? ential input voltage ? ange gain=pgsags 9 r- /gain 9 r+ /gain v t cpga gain te ? pe ? atu ? e d ? ift ta=- ? 0c~85c 5 pp ? / c te?pe?atu?e senso? t cs senso ? te ? pe ? atu ? e d ? ift ta=- ? 0c~85c 9 r =1. ? 5v ? vgs[1:0]=00 (gain=1) ? vrbufp=0 and vrbufn=0 175 9c rev. 1.10 1? de?e??e? 1?? ?01? rev. 1.10 17 de ? e ?? e ? 1 ?? ? 01 ? HT45F75 body fat scale flash mcu HT45F75 body fat scale flash mcu effective number of bits (enob) av dd =3.3v ? v ref = 1. ? 5v ? f mclk = ? .8mhz ? flms[ ? :0]=000 data rate (sps) 5 19.7 19.8 19. ? 19.7 19.7 19. ? 19. ? 18. ? 10 19. ? 19.3 19.3 19.3 19.3 19.1 18.7 18.1 ? 0 19.0 18.8 18.7 18.9 18.8 18. ? 18. ? 17.5 39 18. ? 18.3 18.3 18.3 18.3 18.1 17.7 17.0 78 18.1 17.9 18.0 17.9 17.9 17. ? 17. ? 1 ? .5 15 ? 17. ? 17. ? 17. ? 17. ? 17.3 17.1 1 ? . ? 15.9 313 15.8 15.8 15.9 15.8 15.9 15.9 15.8 15.3 ?? 5 1 ? .1 1 ? .0 1 ? .0 1 ? .1 1 ? .1 1 ? .0 1 ? .1 1 ? . ? av dd =3.3v ? v ref = 1. ? 5v ? f mclk = ? .8mhz ? flms[ ? :0]=010 data rate (sps) 1 ? 19. ? 18.8 18.7 18.8 18.8 18.7 18.9 18.1 ?? 19.0 18.3 18.3 18.3 18.3 18. ? 17.9 17.3 ? 9 18.5 17.8 17.8 17.8 17.9 17.7 17. ? 1 ? .8 98 18. ? 18. ? 18.1 18. ? 18.1 17.8 17. ? 1 ? . ? 195 17.9 17.8 17.8 17.8 17. ? 17.3 1 ? .7 15.9 391 17. ? 17. ? 17. ? 17. ? 17.1 1 ? .8 1 ? . ? 15. ? 781 1 ? . ? 1 ? .1 1 ? .1 1 ? .1 1 ? .1 15.9 15.5 1 ? .8 15 ? 3 1 ? .5 1 ? .5 1 ? .5 1 ? . ? 1 ? .5 1 ? .5 1 ? .3 1 ? .0 operational amplifer electrical characteristics (body fat circuit) ta= ? 5c sy??ol pa?a?ete? test conditions min. typ. max. unit v dd conditions v dd supply voltage ? . ? 5.5 v i ?? ?xsso&xuuhqw3hu?ljqdopsolhu 5v io=0a 150 3 ? 0 500 op0? op? sr slew rate at unity gain 3v r l =100k& l =100pf 7.5 v/s gbw gain bandwidth p ? odu ? t 3v r l =100k& l =100pf ? mhz op1 sr slew rate at unity gain 3v r l =100k& l =100pf 7.5 v/s gbw gain bandwidth p ? odu ? t 3v r l =100k& l =100pf 5 mhz rev. 1.10 18 de ? e ?? e ? 1 ?? ? 01 ? rev. 1.10 19 de?e??e? 1?? ?01? HT45F75 body fat scale flash mcu HT45F75 body fat scale flash mcu oeo eset chaactestcs ta= ? 5c sy??ol pa?a?ete? test conditions min. typ. max. unit v dd conditions v por v dd sta ? t voltage to ensu ? e powe ? -on reset 100 ? v rr vdd v dd raising rate to ensu ? e powe ? -on reset 0.035 v/ ? s t por mini ? u ? ti ? e fo ? v dd stays at v por to ensu ? e powe ? -on reset 1 ? s system architecture a key factor in the high-performanc e features of the holtek range of microcontrollers is attributed to their inte rnal system architecture. the range of the device take advantag e of the usual features found within ris c microcontrollers providing increas ed s peed of operation and enhanced performance. the pi pelining sc heme i s i mplemented i n suc h a wa y t hat i nstruction fe tching a nd i nstruction execution are overlapped, hence instructions are ef fectively executed in one or two cycles for most of the standard or extended instructions respectively . the exceptions to this are branch or call instructions which need one more cycle. an 8-bit wide alu is used in practically all instruction set operations, which carries out arithm etic operations, logic operations, rotation, increment, decrement, branch decisions, etc. the internal data path is simplifed by moving data through the accumulator and the alu. certain internal registers are implemented in the data memory and can be directly or indirectly addresse d. the simple addressi ng methods of these registers along with additi onal architectural features ensure that a minimum of external components is required to provide a functional i/o and a/d control system with maximum reliability and flexibility . this makes the device suitable for low-cost, high-volume production for controller applications. the main system clock, derived from either a hxt , lxt , hirc or lirc oscillator is subdivided into four internall y generated non-overlapping clocks, t1~t4. the program counter is incremented at the beginning of the t1 clock during which time a new instruction is fetched. the remaining t2~t4 clocks carry out the decoding and execution functions. in this way , one t1~t4 clock cycle forms one instruction cycle. although the fetching and execution of instructions takes place in consecutive instruction cycles, the pipelining structure of the microcontroller ensures that instructions are ef fectively executed in one instruction cycle. the exce ption to this are instructions where the content s of the program counter are changed, such as subroutine calls or jumps, in which case the instruction will take one more instruction cycle to execute. rev. 1.10 18 de?e??e? 1?? ?01? rev. 1.10 19 de ? e ?? e ? 1 ?? ? 01 ? HT45F75 body fat scale flash mcu HT45F75 body fat scale flash mcu ? ? ? ? ? system clocking and pipelining for instructions involving branches, such as jump or call instructions, two machine cycles are required to complete instruction execution. an extra cycle is required as the program takes one cycle to frst obtain the actual jump or call address and then another cycle to actually execute the branch. the requirement for this extra cycle should be taken into account by programmers in timing sensitive applications. ? ? ? ? ? ? ? ? ? ? instruction fetching program counter during program execution, the program counter is used to keep track of the address of the next instruction to be executed. it is automatically incremented by one each time an instruction is ex ecuted except for instructions, such as jmp or call that demands a jump to a non-consecutive program memory address. only the lower 8 bits, known as the program counter low register , are directly addressable by the application program. when executing instructions requiring jumps to non-consecutive addresses such as a jump instruction, a subroutine call, interrupt or reset, etc., the microcontroller manages program control by loading the required address into the program counter . for conditional skip instructions, once the condition has been met, the next instruction, which has already been fetched during the present instruction execution, is discarded and a dummy cycle takes its place while the correct instruction is obtained. pc11~pc8 pcl7~pcl0 p?og?a? counte? the lower byte of the program counter , known as the program counter low register or pcl, is available for program control and is a readable and writeable register . by transferring data directly into this register , a short program jump can be executed directly , however , as only this low byte is available for manipulation, the jumps are limited to the present page of memory , that is 256 locations. when such program jumps are executed it should also be noted that a dummy cycle will be inserted. manipulating the pcl register may cause program branching, so an extra cycle is needed to pre-fetch. rev. 1.10 ? 0 de ? e ?? e ? 1 ?? ? 01 ? rev. 1.10 ?1 de?e??e? 1?? ?01? HT45F75 body fat scale flash mcu HT45F75 body fat scale flash mcu stac this is a special part of the memory which is used to save the contents of the program counter only. the stack is or ganized into 8 levels and neither part of the data nor part of the program space, and is neither readable nor writeable. the activated level is indexed by the stack pointer , and is neither readable nor writeable. at a subroutine call or interrupt acknowledge signal, the contents of the program counter are pushed onto the stack. at the end of a subroutine or an interrupt routine, signaled by a return instruction, ret or reti, the program counter is restored to its previous value from the stack. after a device reset, the stack pointer will point to the top of the stack. if the stack is full and an enabled interrupt takes place, the interrupt request fag will be recorded but the acknowledge signal will be inhibited. when the stack pointer is decremented, by ret or reti, the interrupt will be serviced. this feature prevents stack overfow allo wing the programmer to use the struct ure more easily . however , when the stack is full, a call subroutine instruction can still be execu ted which will result in a stack overfow . precautions should be taken to avoid such cases which might cause unpredictable program branching. if the stack is overfow, the frst program counter save in the stack will be lost. arithmetic and logic unit ? alu the arith metic-logic unit or alu is a critical area of the microcontrol ler that carries out arithmetic and logic operations of the instructi on set. connected to the main micro controller data bus, the alu receives related ins truction codes and performs the required arithmetic or logical operations after which the result will be placed in the specifed register . as these alu calculation or operations may result in carry , borrow or other status changes, the status register will be correspondingly updated to refect these changes. the alu supports the following functions: ? arithmetic operations: add, addm, adc, adcm, sub, subm, sbc, sbcm, daa, ladd, laddm, ladc, ladcm, lsub, lsubm, lsbc, lsbcm, ldaa ? logic operations: and, or, xor, andm, orm, xorm, cpl, cpla, land, landm, lor, lorm, lxor, lxorm, lcpl, lcpla ? rotation rra, rr, rrca, rrc, rla, rl, rlca, rlc, lrr, lrra, lrrca, lrrc, lrla, lrl, lrlca, lrlc ? increment and decrement inca, inc, deca, dec, linca, linc, ldeca, ldec ? branch decision, jmp, sz, sza, snz, siz, sdz, siza, sdza, call, ret, reti, lsnz, lsz, lsza, lsiz, lsiz, lsdz, lsdza rev. 1.10 ?0 de?e??e? 1?? ?01? rev. 1.10 ? 1 de ? e ?? e ? 1 ?? ? 01 ? HT45F75 body fat scale flash mcu HT45F75 body fat scale flash mcu flash oa meoy the program memory is the locatio n where the user code or program is stored. for this device the program memory is flash type, which means it can be programmed and re-programmed a lar ge number o f t imes, a llowing t he u ser t he c onvenience o f c ode m odification o n t he sa me d evice. by using the appropriate programming tools, this flash device of fers users the flexibility to conveniently debug and develop their applications while also of fering a means of feld programming and updating. the progra m me mory ha s a c apacity of 4k16 bi ts. t he progra m me mory i s a ddressed by t he program counter and also contains data, table information and interrupt entries. t able data, which can be setup in any location within the program memory , is addressed by a separate table pointer register. reset inte??upt ve?to?s 1? ?its 0000h 000?h 00??h 0fffh p?og?a? me?o?y st?u?tu?e spe?ial ve?to?s within the program memory , certai n locations are reserved for the reset and interrupts. the location 000h is reserved for use by the device reset for program initialisation. after a device reset is initiated, the program will jump to this location and begin execution. any location within the program memory can be defned as a look-up table where programmers can store fxed data. t o use the look-up table, the table pointer must frst be setup by placing the address of the look up data to be retrieved in the table pointer register , tblp and tbhp . these registers defne the total address of the look-up table. after setting up the table pointer, the table data can be retrieved from the program memory using the corresponding table read instruction such as t abrd [m] or t abrdl [m] respectively when the memory [m] is located in sector 0. if the memory [m] is located in other sectors, the data can be retrieved from the program memory using the corresponding extended table read instruction such as ltabrd [m] or l tabrdl [m] respectively . when the instruction is executed, the lower order table byte from the program memory will be transferred to the user defned data memory register [m] as specifed in the instruction. the higher order table data byte from the program memory will be transferred to the tblh special register. rev. 1.10 ?? de ? e ?? e ? 1 ?? ? 01 ? rev. 1.10 ?3 de?e??e? 1?? ?01? HT45F75 body fat scale flash mcu HT45F75 body fat scale flash mcu the accompanying diagram illustrates the addressing data fow of the look-up table. table program example the following example shows how the table pointer and table data is defned and retrieved from the microcontroller . this example us es raw table data located in the p rogram m emory w hich is stored there using the org statement. the value at this org statement is 0f00h which refers to the start address of the last page within the 4k program memory of the microcontroller . the table pointer low byte register is setup here to have an initial value of 06h. this will ensure that the frst data read from the data table will be at the program memory address 0f06h or 6 locations after the start of the last page. note that the value for the table pointer is referenced to the frst address specifed by tblp and tbhp if the t abrd [m] or l tabrd [m] instruction is being used. the high byte of the table data which in this case is equal to zero will be transferred to the tblh register automatically when the tabrd [m] or ltabrd [m] instruction is executed. because the tblh register is a read/write register and can be restored, care should be taken to ensure its protection if both the main routine and interrupt s ervice routine us e table read instructions. if using the table read instructions, the interrupt service routines may change the value of the tblh and subsequently cause errors if used again by the main routine. as a rule it is recommended that simultaneous use of the table read instructions should be avoided. however , in situations where simultaneous use cannot be avoided, the interrupts should be disabled prior to the execution of any main routine table-read instructions. note that all table related instructions require two instruction cycles to complete their operation. tempreg1 db ? ; temporary register #1 tempr eg2 db ? ; temporary register #2 : : mov a,06h ; initialise low table pointer - note that this address is referenced mov tblp,a ; to the last page or the page that tbhp pointed mov a,0fh ; initialise high table pointer mov tbhp,a : : tabrd tempreg1 ; transfers value in table referenced by table pointer data at program ; memory address 0f06h transferred to tempreg1 and tblh dec tblp ; reduce value of table pointer by one tabrd tempreg2 ; transfers value in table referenced by table pointer ; data at program memory address 0f05h transferred to ; tempreg2 and tblh in this example the data 1ah is ; transferred to tempreg1 and data 0fh to register tempreg2 : : org 0f00h ; sets initial address of program memory dc 00ah, 00bh, 00ch, 00dh, 00eh, 00fh, 01ah, 01bh : : rev. 1.10 ?? de?e??e? 1?? ?01? rev. 1.10 ? 3 de ? e ?? e ? 1 ?? ? 01 ? HT45F75 body fat scale flash mcu HT45F75 body fat scale flash mcu cct oa c the provision of flash type program memory provides the user with a means of convenient and easy upgrades a nd m odifcations t o t heir p rograms o n t he sa me d evice. as a n a dditional c onvenience, holtek has provided a means of programming the microcontroller in-circuit using a 4-pin interface. this provides manufacturers with the possibility of manufacturing their circuit boards complete with a programmed or un-programmed microcontroller , and then programming or upgrading the program at a later stage. this enables product manufacturers to easily keep their manufactured products supplied with the latest program releases without removal and re-insertion of the device. the holtek flash mcu to w riter programming pin correspondence table is as follows: icpda pa0 p ? og ? a ?? ing se ? ial data/add ? ess icpck pa ? p ? og ? a ?? ing clo ? k vdd vdd powe ? supply vss vss g ? ound the program memory can be programmed serially in-circuit using this 4-wire interface. data is downloaded and uploaded serially on a single pin with an additional line for the clock. t wo additional l ines a re r equired f or t he p ower su pply. t he t echnical d etails r egarding t he i n-circuit programming of the device are beyond the scope of this document and will be supplied in supplementary literature. during the programming process, taking control of the icpda and icpck pins for data and clock programming purposes. the user must there take care to ensure that no other outputs are connected to these two pins. note: * may be resistor or capacito r. the resistance of * must be great er than 1k or the capacitance of * must be less than 1nf. there i s a n e v c hip n amed ht 45v75 wh ich i s u sed t o e mulate t he ht 45f75 d evice. t he e v chip device also provides an on-chip debug function to debug the real mcu device during the development proces s. the ev chip and the real m cu device are almos t functionally compatible except for on-chip debug function. users can use the ev chip device to emulate the real chip device behavior by connecting the ocdsda and ocdsck pins to the holtek ht-ide development tools. the ocdsda pin is the ocds data/address input/output pin while the ocdsck pin is the oc ds c lock i nput p in. w hen u sers u se t he e v c hip f or d ebugging, o ther f unctions wh ich a re shared with the ocdsda and ocdsck pins in the device will have no ef fect in the ev chip. rev. 1.10 ?? de ? e ?? e ? 1 ?? ? 01 ? rev. 1.10 ?5 de?e??e? 1?? ?01? HT45F75 body fat scale flash mcu HT45F75 body fat scale flash mcu however, the two ocds pins which are pin-shared with the icp programming pins are still used as the flash memory programming pins for icp . for more detailed ocds information, refer to the corresponding document named holtek e-link for 8-bit mcu ocds users guide. ocdsda ocdsda on-chip de ? ug suppo ? t data/add ? ess input/output ocdsck ocdsck on-chip de ? ug suppo ? t clo ? k input vdd vdd powe ? supply vss vss g ? ound in appli?ation p?og?a??ing C iap the device of fers iap function to update data or application program to flash rom. users can defne any rom location for iap , but there are some features which user must notice in using iap function. ? erase block: 256 words/block ? writing: 4 words/time ? reading: 1 word/time the address registers, f arl and f arh, and the data registers, fd0l/fd0h, fd1l/fd1h, fd2l/ fd2h, fd3l/fd3h, located in all data memory sectors, together with the control registers, fc0 and fc1, located in data memory sector 1 are the corresponding flash access registers for iap . as indirect addressing is the only way to access the fc0 and fc1 registers, all read and write operations to the registers must be performed using the indirect addressing register , iar1 or iar2, and the memory pointer pair, mp1l/mp1h or mp2l/mp2h. because the fc0 and fc1 control registers are located at the address of 28h~29h in data memory sector 1, the desired value ranged from 28h to 29h must be written into the mp1l or mp2l memory pointer low byte and the value 01h must also be written into the mp1h or mp2h memory pointer high byte. ? na ? e cfwen fmod ? fmod1 fmod0 fwpen fwt frden frd r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 1 1 1 0 0 0 0 bit 7 cfwen : flash memory w rite enable control 0: flash memory write function is disabled 1: flash memory write function has been successfully enabled when this bit is cleared to 0 by application program, the flash memory write function is dis abled. n ote that w riting a 1 into this bit results in no action. this bit is us ed to indicate that the flash memory write function status. when this bit is set to 1 by hardware, it means that the f lash memory w rite function is enabled s uccessfully. otherwise, the flash memory write function is disabled as the bit content is zero. bit 6~4 fmod2~fmod0 : mode selection 000: w rite program memory 001: block erase program memory 010: reserved 011: read program memory 100: reserved 101: reserved 110: fwrn mode flash memory write function enable mode 111: reserved rev. 1.10 ?? de?e??e? 1?? ?01? rev. 1.10 ? 5 de ? e ?? e ? 1 ?? ? 01 ? HT45F75 body fat scale flash mcu HT45F75 body fat scale flash mcu bit 3 : flash memory w rite procedure enable control 0: disable 1: enable when this bit is set to 1 and the fmod feld is set to 1 10, the iap controller will execute the flash memory write function enable procedure. once the flash memory write func tion i s suc cessfully e nabled, i t i s not ne cessary t o set t he fw pen bi t a ny more. bit 2 : flash rom write control bit 0: do not initiate flash memory write or flash memory write process is completed 1: initiate flash memory write process this bit is set by software and cleared by hardware when the flash memory write process is completed. bit 1 : flash memory read enabled bit 0: flash memory read disable 1: flash memory read enable bit 0 : flash memory read control bit 0: do not initiate flash memory read or flash memory read process is completed 1: initiate flash memory read process this bi t i s se t by soft ware a nd c leared by hardware whe n t he fl ash m emory rea d process is completed. ? fc1 register bit 7 6 5 4 3 2 1 0 na ? e d7 d ? d5 d ? d3 d ? d1 d0 r/w r r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~0 : whole chip reset when user writes a specific value of 55h to this register , it will generate a reset signal to reset whole chip. ? farl register bit 7 6 5 4 3 2 1 0 na ? e a7 a ? a5 a ? a3 a ? a1 a0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~0 flash memory address [7:0] ? farh register bit 7 6 5 4 3 2 1 0 na ? e a15 a1 ? a13 a1 ? a11 a10 a9 a8 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~0 flash memory address [15:8] ? fd0l register bit 7 6 5 4 3 2 1 0 na ? e d7 d ? d5 d ? d3 d ? d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~0 the frst flash memory data [7:0] rev. 1.10 ?? de ? e ?? e ? 1 ?? ? 01 ? rev. 1.10 ?7 de?e??e? 1?? ?01? HT45F75 body fat scale flash mcu HT45F75 body fat scale flash mcu ? na ? e d15 d1 ? d13 d1 ? d11 d10 d9 d8 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 %lw a 7kh uvw )odvk 0hpru gdwd > ? na ? e d7 d ? d5 d ? d3 d ? d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 %lw a 7kh vhfrqg )odvk 0hpru gdwd > ? na ? e d15 d1 ? d13 d1 ? d11 d10 d9 d8 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 %lw a 7kh vhfrqg )odvk 0hpru gdwd > ? na ? e d7 d ? d5 d ? d3 d ? d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 %lw a 7kh wklug )odvk 0hpru gdwd > ? na ? e d15 d1 ? d13 d1 ? d11 d10 d9 d8 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 %lw a 7kh wklug )odvk 0hpru gdwd > ? na ? e d7 d ? d5 d ? d3 d ? d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 %lw a 7kh irxuwk )odvk 0hpru gdwd > ? na ? e d15 d1 ? d13 d1 ? d11 d10 d9 d8 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 %lw a 7kh irxuwk )odvk 0hpru gdwd > rev. 1.10 ?? de?e??e? 1?? ?01? rev. 1.10 ? 7 de ? e ?? e ? 1 ?? ? 01 ? HT45F75 body fat scale flash mcu HT45F75 body fat scale flash mcu flash meoy te fcto ale ocede in orde r t o a llow use rs t o c hange t he fl ash m emory da ta t hrough t he iap c ontrol re gisters, use rs must frst enable the flash memory write operation by the following procedure: 1. w rite 110 into the fmod2~fmod0 bits to select the fwen mode. 2. set the fwpen bit to 1. the step 1 and step 2 can be executed simultaneously. 3. the pattern data with a sequence of 00h, 04h, 0dh, 09h, c3h and 40h must be written into the fd1l, fd1h, fd2l, fd2h, fd3l and fd3h registers respectively. 4. a counter with a time-out period of 300s will be activated to allow users writing the correct pattern data into the fd1l/fd1h~fd3l/fd3h register pairs. the counter clock is derived from lirc oscillator. 5. if the counter overfows or the pattern data is incorrect, the flash memory write operation will not be ena bled a nd use rs m ust aga in repe at t he a bove proce dure. the n t he fw pen bi t wi ll automatically be cleared to 0 by hardware. 6. if the pattern data is correct before the counter overfows, the flash memory write operation will be enable d and the fwpen bit will automatically be cleared to 0 by hardware. the cfwen bit will also be set to 1 by hardware to indicate that the flash memory write operation is successfully enabled. 7. once the flash memory write operation is enabled, the user can change the flash rom data through the flash control register. 8. t o disable the flash memory write operation, the user can clear the cfwen bit to 0. flash me?o?y w?ite fun?tion ena?le p?o?edu?e set fmod [?:0] =110 & fwpen=1 sele?t fwen ?ode & sta?t flash w?ite ha?dwa?e a?tivate a ?ounte? w?tie the following patte?n to flash data ?egiste?s fd1l= 00h ? fd1h = 0?h fd?l= 0dh ? fd?h = 09h fd3l= c3h ? fd3h = ?0h is patte?n is ?o??e?t ? is ?ounte? ove?flow ? fwpen=0 ? yes no no yes su??ess end no yes failed fwpen=0 & cfwen=0 cfwen = 1 flash me?o?y w?ite fun?tion ena?le p?o?edu?e rev. 1.10 ? 8 de ? e ?? e ? 1 ?? ? 01 ? rev. 1.10 ?9 de?e??e? 1?? ?01? HT45F75 body fat scale flash mcu HT45F75 body fat scale flash mcu flash meoy eadte ocede after the flash memory write functi on is successfully enabled through the preceding iap procedure, users m ust fr st e rase t he c orresponding fl ash m emory b lock a nd t hen i nitiate t he fl ash m emory write operation. since the number of the block erase operation is 256 words per block, the available block erase address is only specifed by f arh register and the content in the f arl register is not used to specify the block address. 0 0000 0000 xxxx xxxx 1 0000 0001 xxxx xxxx ? 0000 0010 xxxx xxxx 3 0000 0011 xxxx xxxx ? 0000 0100 xxxx xxxx 5 0000 0101 xxxx xxxx ? 0000 0110 xxxx xxxx 7 0000 0111 xxxx xxxx 8 0000 1000 xxxx xxxx 9 0000 1001 xxxx xxxx 10 0000 1010 xxxx xxxx 11 0000 1011 xxxx xxxx 1 ? 0000 1100 xxxx xxxx 13 0000 1101 xxxx xxxx 1 ? 0000 1110 xxxx xxxx 15 0000 1111 xxxx xxxx x: dont ? a ? e e?ase blo?k nu??e? and sele?tion rev. 1.10 ?8 de?e??e? 1?? ?01? rev. 1.10 ? 9 de ? e ?? e ? 1 ?? ? 01 ? HT45F75 body fat scale flash mcu HT45F75 body fat scale flash mcu read flash me?o?y clea? frden ?it end read finish ? yes no set fmod [?:0]=011 & frden=1 set flash add?ess ?egiste?s farh=xxh? farl=xxh frd=0 ? yes no read data value: fd0l=xxh? fd0h=xxh set frd=1 read flash me?o?y p?o?edu?e rev. 1.10 30 de ? e ?? e ? 1 ?? ? 01 ? rev. 1.10 31 de?e??e? 1?? ?01? HT45F75 body fat scale flash mcu HT45F75 body fat scale flash mcu w?ite flash me?o?y flash me?o?y w?ite fun?tion ena?le p?o?edu?e set fwt=1 fwt=0 ? no set blo?k e?ase add?ess: farh/farl set fmod [?:0]=001 & fwt=1 sele?t "blo?k e?ase ?ode" & initiate w?ite ope?ation fwt=0 ? yes no clea? cfwen=0 end w?ite finish ? no set fmod [?:0]=000 sele?t "w?ite flash mode" set w?ite sta?ting add?ess: farh/farl w?ite data to data ?egiste?: fd0l/fd0h? fd1l/fd1h fd?l/fd?h? fd3l/fd3h yes yes w?ite flash me?o?y p?o?edu?e note: when the fwt or frd bit is set to 1, the mcu is stopped. rev. 1.10 30 de?e??e? 1?? ?01? rev. 1.10 31 de ? e ?? e ? 1 ?? ? 01 ? HT45F75 body fat scale flash mcu HT45F75 body fat scale flash mcu m ata meoy the data memory is a volatile area of 8-bit wide ram internal memory and is the location where temporary information is stored. divided into three types, the frst of these is an area of ram where special function registers are located. t hese r egisters h ave fx ed l ocations a nd a re n ecessary f or c orrect o peration o f t he d evice. many of these registers can be read from and written to directly under program control, however , some remain protecte d from use r manipulation. the second area of data memory is reserved for general purpose use . al l l ocations wi thin t his a rea a re re ad a nd wri te a ccessible unde r progra m control. t he t hird a rea i s use d for t he si ne pa ttern func tion. t he a ddresses of t he si ne pa ttern memory area overlap those in the general purpose data memory area. the da ta me mory i s subdi vided i nto se veral se ctors, a ll of wh ich a re i mplemented i n 8-b it wi de ram. each of the d ata m emory s ector is categorized into tw o types , the s pecial p urpose d ata memory and the general purpose data memory . while the 80h~bfh of sector 2 is sine pattern memory. the start address of the data memory for the device is the address 00h while the start address of the general purpose data memory , or sine pattern memory is the address 80h. the special purpose data memory registers are accessible in all sectors, with the exception of the eec register at address 40h, and the fc0 and fc1 registers at addresses 28h~29h, which are only accessible in sector 1. switching between the dif ferent data memory sectors is achieved by setting the memory pointers to the correct value. gene ? al pu ? pose: ? 5 ? 8 0: 80h~ffh ? : 80h~bfh (fo ? sine patte ? n) 3: 80h~ffh se?to? ? 00h 7fh 80h ffh spe?ial pu?pose data me?o?y gene?al pu?pose data me?o?y se?to? 0 se?to? ? sine patte?n me?o?y eec in se?to? 1 bfh fc0~fc1 in se?to? 1 data me?o?y st?u?tu?e rev. 1.10 3 ? de ? e ?? e ? 1 ?? ? 01 ? rev. 1.10 33 de?e??e? 1?? ?01? HT45F75 body fat scale flash mcu HT45F75 body fat scale flash mcu eeal ose ata meoy there are 256 bytes of general purpose data memory which are arranged in 80h~ffh of sector 0 and sector 3. all microcontroller programs require an area of read/write memory where temporary data can be stored and retrieved for use later . it is this area of ram memory that is known as general purpose data memory. this area of data memory is fully accessible by the user programing for bot h re ading and writing operations. by using the bit operation instructions individual bits can be set or reset under program control giving the user a lar ge range of fexibility for bit manipulation in the data memory. this area of data memory is where registers, necessary for the correct operation of the microcontroller, are stored. most of the registers are both readable and writeable but some are protected and are readable only , the details of which are located under the relevant special function register section. note that for locat ions that are unused, any read instruction to these addresses will return the value 00h. rev. 1.10 3? de?e??e? 1?? ?01? rev. 1.10 33 de ? e ?? e ? 1 ?? ? 01 ? HT45F75 body fat scale flash mcu HT45F75 body fat scale flash mcu 00h iar 0 01h mp 0 0?h iar 1 03h mp 1l 0?h 05h acc 0?h pcl 07h tblp 08h tblh 09h tbhp 0 ah status 0 bh 0 ch adrl 0 dh ptm 1 dh 0 eh 0 fh 10h intc 0 11h ptm 1 al 1?h 19h mfi 0 18h mfi 1 1 bh 1 ah 1 dh 1 ch 1 fh intc ? pdc 13h 1?h tm 0c1 15h tm 0 dl 1?h 17h ptm 1 ah tm 0 dh ptm ? rph pbc lvrc ctrl ?0h ?1h ??h ?9h ?8h ? bh ? ah ? dh ? ch ? fh ? eh ?3h ??h ?5h ??h ?7h eea ptm ?c0 ptm ?c1 ptm ? dl ptm ? dh ptm ? al ptm ? ah ?0h ?1h ??h ?3h ??h ?5h ??h ?7h ?8h ?9h ? ah ? bh ? ch ? dh ? eh ? fh 50h 51h 5?h 53h 5?h tm 0 al adrh eed 1 eh tm 0c0 ctrl 0 55h 5?h ?0h ?1h ??h ?3h ??h ?5h ??h ?7h ?8h ?9h ? ah ? bh ? ch ? dh ? eh ? fh 70h adcr 0 adcr 1 30h 31h 3?h 38h 3 ch 33h 3?h 35h 3?h 37h adcs adrm ptm 1c0 ptm 1c1 ptm 1 dl 3 bh 39h 3 ah 71h 7?h 73h 7?h 75h 7?h pac pbpu pa 3 dh 3 fh 3 eh mp 1h iar ? mp ?l mp ?h mfi 3 intc 1 mfi ? pawu papu pb pcpu pc pcc pdpu pd tm 1 ah ptm 1 rpl pwrc sledc 0 sledc 1 pgacs pgac 0 pgac 1 usr ucr 1 ucr ? brg 57h txrrxr 58h 59h irctrl 0 5 ah irctrl 1 5 bh 5 ch 5 dh 5 eh 5 fh simc 0 simc 1 sima / simc ? simd simtoc farl farh fd 0l fd 0h fd 1l fd 1h fd ?l fd ?h fd 3l fd 3h sgc sgn sgdnr opac swc daco ftrc ptm 1 rph ptm ? rpl smod lvdc tbc integ wdtc 78h 7 ch 77h 7 bh 79h 7 ah 7 dh 7 fh 7 eh : unused ? ?ead as 00h fc 0 fc 1 eec se?to? 0???3 se?to? 1 se?to? 0???3 se?to? 1 spe?ial pu?pose data me?o?y rev. 1.10 3 ? de ? e ?? e ? 1 ?? ? 01 ? rev. 1.10 35 de?e??e? 1?? ?01? HT45F75 body fat scale flash mcu HT45F75 body fat scale flash mcu secal fcto este escto most of the special function register details will be described in the relevant functional section, however several registers require a separate description in this section. the indirect addressing registers, iar0, iar1 and iar2, although having their locations in normal ram r egister sp ace, d o n ot a ctually p hysically e xist a s n ormal r egisters. t he m ethod o f i ndirect addressing for ram da ta m anipulation use s t hese indi rect addre ssing re gisters a nd me mory pointers, i n c ontrast t o di rect m emory a ddressing, where t he a ctual m emory a ddress i s spe cifed. actions on t he iar0, iar1 a nd iar2 re gisters wi ll re sult i n no a ctual re ad or writ e ope ration t o these registers but rather to the memory location specifed by their corresponding memory pointers, mp0, mp1l/mp1h or mp2l/mp2h. acting as a pair , iar0 and mp0 can together access data only from sector 0 while the iar1 register together with the mp1l/mp1h register pair and iar2 register together with the mp2l/mp2h register pair can access data from any data memory sector . as the indirec t addressing re gisters are not physi cally i mplemented, rea ding t he indirec t addressing registers will return a result of 00h and writing to the registers will result in no operation. five memory pointers, known as mp0, mp1l, mp1h, mp2l, mp2h, are provided. these memory pointers are physically implemente d in the data memory and can be manipulated in the same way as n ormal r egisters p roviding a c onvenient wa y wi th wh ich t o a ddress a nd t rack d ata. w hen a ny operation to the relevant indirect addressing registers is carried out, the actual address that the microcontroller is directed to is the address specifed by the related memory pointer . mp0, together with indirect addressing register , iar0, are used to access data from sector 0, while mp1l/mp1h together with iar1 and mp2l/mp2h together with iar2 are used to access data from all sectors according t o t he c orresponding mp1h or mp2h regi ster. di rect addre ssing ca n be use d i n a ll sectors using the corresponding instruction which can address all available data memory space. the following example shows how to clear a section of four data memory locations already defned as locations adres1 to adres4. data .section data adres1 d b ? adres2 d b ? adres3 d b ? adres4 d b ? block d b ? code .section at 0 code org 00h start: m ov a, 04h ; setup size of block m ov block, a mov a , o ffset ad res1 ; a ccumulator l oaded w ith f rst r am ad dress mov m p0, a ; s etup m emory po inter wi th f rst r am a ddress loop: clr i ar0 ; c lear t he d ata a t ad dress d efned b y m p0 i nc mp0 ; increment memory pointer s dz block ; check if last memory location has been cleared jm p loop continue: rev. 1.10 3? de?e??e? 1?? ?01? rev. 1.10 35 de ? e ?? e ? 1 ?? ? 01 ? HT45F75 body fat scale flash mcu HT45F75 body fat scale flash mcu dect ddess oa ale data .section data adres1 d b ? adres2 d b ? adres3 d b ? adres4 d b ? block d b ? code .section at 0 code org 00h start: m ov a, 04h ; setup size of block m ov block, a mov a, 01h ; setup the memory sector mov mp1h, a mov a , o ffset ad res1 ; a ccumulator l oaded w ith f rst r am ad dress mov m p1l, a ; s etup m emory po inter wi th f rst r am a ddress loop: clr i ar1 ; c lear t he d ata a t a ddress d efned b y m p1l inc m p1l ; i ncrement m emory po inter m p1l s dz block ; check if last memory location has been cleared jm p loop continue: the important point to note here is that in the example shown above, no reference is made to specifc data memory addresses. data .section data temp db ? code .section at 0 code org 00h start: l mov a, [m] ; move [m] data to acc l sub a, [m+1] ; compare [m] and [m+1] data snz c ; [m]>[m+1]? jmp c ontinue ; no lmov a , [m] ; yes, exchange [m] and [m+1] data mov t emp, a lmov a, [m+1] lmov [m], a mov a , temp lmov [m+1], a continue: note: here m is a data memory address located in any data memory sectors. for example, m=1f0h, it indicates address 0f0h in sector 1. the a ccumulator is central to the operation of any microcontroller and is clos ely related w ith operations carried out by the alu. the accumulator is the place where all intermediate results from the alu are stored. w ithout the accumulator it would be necessary to write the result of each c alculation or l ogical ope ration suc h a s a ddition, subt raction, shi ft, e tc., t o t he da ta me mory resulting i n highe r program ming and t iming overheads. da ta t ransfer operat ions usual ly i nvolve the t emporary st orage func tion of t he ac cumulator; for e xample, wh en t ransferring da ta be tween one user -defined register and another , it is necessary to do this by passing the data through the accumulator as no direct transfer between two registers is permitted. rev. 1.10 3 ? de ? e ?? e ? 1 ?? ? 01 ? rev. 1.10 37 de?e??e? 1?? ?01? HT45F75 body fat scale flash mcu HT45F75 body fat scale flash mcu oa cote o este c to provide additional program control functions, the low byte of the program counter is made accessible to programmers by locating it within the special purpose area of the data memory . by manipulating this register , direct jumps to other program locations are easily implemented. loading a value directly into this pcl register will cause a jump to the specifed program memory location, however, as the register is only 8-bit wide, only jumps within the current program memory page are permitted. when such operations are used, note that a dummy cycle will be inserted. these three special function registers are used to cont rol operation of the look-up table which is stored i n t he progra m me mory. t blp a nd t bhp a re t he t able poi nter a nd i ndicates t he l ocation where the table data is located. their value must be setup before any table read commands are executed. their value can be changed, for example using the inc or dec instructions, allowing for easy table data pointing and reading. tblh is the location where the high order byte of the table data is stored afte r a table read data instruction has been executed. note that the lower order table data byte is transferred to a user defned location. this 8-bit register contains the sc fag, cz fag, zero fag (z), carry fag (c), auxiliary carry fag (ac), overfow fag (ov), power down fag (pdf), and watchdog time-out fag (t o). these arithmetic/ logical o peration a nd sy stem m anagement fa gs a re u sed t o r ecord t he st atus a nd o peration o f t he microcontroller. with the exceptio n of the t o and pdf fags, bits in the status register can be altered by instructions like most other registers. any data written into the status register will not change the t o or pdf fag. in addition, operations related to the status register may give dif ferent results due to the dif ferent instruction operati ons. the t o fag can be af fected only by a system power -up, a wdt time-out or by executing the clr wdt or hal t instruction. the pdf fag is af fected only by executing the halt or clr wdt instruction or during a system power-up. the z, ov, ac, c, sc and cz fags generally refect the status of the latest operations. ? c is set if an operation results in a carry during an addition operation or if a borrow does not take place during a subtraction operation; otherwise c is cleared. c is also af fected by a rotate through carry instruction. ? ac is set if an operation results in a carry out of the low nibbles in addition, or no borrow from the high nibble into the low nibble in subtraction; otherwise ac is cleared. ? z is set if the result of an arithmetic or logical operation is zero; otherwise z is cleared. ? ov is set if an operation results in a carry into the highest-order bit but not a carry out of the highest-order bit, or vice versa; otherwise ov is cleared. ? pdf is cleared by a system power -up or executing the clr wdt instruction. pdf is set by executing the halt instruction. ? to is cle ared by a system power -up or executing the clr wdt or hal t instruction. to is set by a wdt time-out. ? cz is the operational result of dif ferent flags for dif ferent instructions. refer to register defnitions for more details. ? sc is the result of the xor operation which is performed by the ov fag and the msb of the current instruction operation result. rev. 1.10 3? de?e??e? 1?? ?01? rev. 1.10 37 de ? e ?? e ? 1 ?? ? 01 ? HT45F75 body fat scale flash mcu HT45F75 body fat scale flash mcu in additio n, on entering an interrup t sequence or executing a subroutine call, the status register will not be pushed onto the stack automatically . if the contents of the status registers are important and if the subroutine can corrupt the status register, precautions must be taken to correctly save it. na ? e sc cz to pdf ov z ac c r/w r r r r r/w r/w r/w r/w por x x 0 0 x x x x x unknown bit 7 sc : xor operation result - performed by the ov fag and the msb of the instruction operation result. bit 6 cz : operational result of different fags for different instructions. for sub/subm/lsub/lsubm instructions, the cz fag is equal to the z fag. for s bc/ s bcm/ ls bc/ ls bcm ins tructions, the cz f ag is the a nd operation result which is performed by the previous operation cz fag and current operation zero fag. for other instructions, the cz fag will not be affected. bit 5 to : w atchdog t ime-out fag 0: after power up or executing the clr wdt or halt instruction 1: a watchdog time-out occurred. bit 4 pdf : power down fag 0: after power up or executing the clr wdt instruction 1: by executing the halt instruction bit 3 ov : overfow fag 0: no overfow 1: an operation results in a carry into the highest-order bit but not a carry out of the highest-order bit or vice versa. bit 2 z : zero fag 0: the result of an arithmetic or logical operation is not zero 1: the result of an arithmetic or logical operation is zero bit 1 ac : auxiliary fag 0: no auxiliary carry 1: an operation results in a carry out of the low nibbles in addition, or no borrow from the high nibble into the low nibble in subtraction bit 0 c : carry fag 0: no carry-out 1: an operation results in a carry during an addition operation or if a borrow does not take place during a subtraction operation c is also affected by a rotate through carry instruction. rev. 1.10 38 de ? e ?? e ? 1 ?? ? 01 ? rev. 1.10 39 de?e??e? 1?? ?01? HT45F75 body fat scale flash mcu HT45F75 body fat scale flash mcu m ata eoy this device contains an area of internal eeprom data memory . eeprom, which stands for electrically e rasable progra mmable re ad onl y me mory, i s by i ts na ture a non-vol atile form of re-programmable memory , with data retention even when its power supply is removed. by incorporating this kind of data memory , a w hole new hos t of application pos sibilities are made available to the designer . the avail ability of eeprom storage allows information such as product identification numbers, calibration values, specific user data, system setup data or other product information to be stored directly within the product microcontroller . the process of reading and writing data to the eeprom memory has been reduced to a very trivial affair. the eeprom data memory capacity is 648 bits for the device. unlike the program memory and ram data memory , the eeprom data memory is not directly mapped into memory space and is therefore not directly addressable in the same way as the other types of memory . read and w rite operations to the eeprom are carried out in single byte operations using an address and a data register in sector 0 and a single control register in sector 1. three registers control the overall operation of the internal eeprom data memory . these are the address register , eea, the data register , eed and a single control register , eec. as both the eea and eed registers are located in all sectors, they can be directly accessed in the same was as any other special function regis ter. the eec regis ter however , being located in sector1, can be read from or written to indirectly using the mp1l/mp1h or mp2l/mp2h memory pointer and indirect addressing register , iar1/iar2. because the eec control register is located at address 40h in sector 1, the mp1l or mp2l memory pointer must frst be set to the value 40h and the mp1h or mp2h memory pointer high byte set to the value, 01h, before any operations on the eec register are executed. eea d5 d ? d3 d ? d1 d0 eed d7 d ? d5 d ? d3 d ? d1 d0 eec wren wr rden rd eeprom registe? list eea registe? bit 7 ? 5 ? 3 ? 1 0 na ? e d5 d ? d3 d ? d1 d0 r/w r/w r/w r/w r/w r/w r/w por x x x x x x x unknown bit 7~6 unimplemented, read as 0 bit 5~0 d5~d0 : data eeprom address data eeprom address bit 5 ~ bit 0 rev. 1.10 38 de?e??e? 1?? ?01? rev. 1.10 39 de ? e ?? e ? 1 ?? ? 01 ? HT45F75 body fat scale flash mcu HT45F75 body fat scale flash mcu este bt 7 5 4 na ? e d7 d ? d5 d ? d3 d ? d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por x x x x x x x x x unknown bit 7~0 d7~d0 : data eeprom data data eeprom data bit 7 ~ bit 0 na ? e wren wr rden rd r/w r/w r/w r/w r/w por 0 0 0 0 bit 7~4 unimplemented, read as 0 bit 3 wren : data eeprom w rite enable 0: disable 1: enable this is the d ata eep rom w rite enable bit w hich mus t be s et high before d ata eeprom write operations are carried out. clearing this bit to zero will inhibit data eeprom write operations. bit 2 wr : eeprom w rite control 0: w rite cycle has fnished 1: activate a write cycle this i s t he da ta e eprom w rite c ontrol b it a nd wh en se t h igh b y t he a pplication program will activ ate a write cycle. this bit will be automatically reset to zero by the hardware after the write cycle has fnished. setting this bit high will have no ef fect if the wren has not frst been set high. bit 1 rden : data eeprom read enable 0: disable 1: enable this is the data eeprom read enable bit which must be set high before data eeprom read operations are carried out. clearing this bit to zero w ill inhibit d ata eeprom read operations. bit 0 rd : eeprom read control 0: read cycle has fnished 1: activate a read cycle this is the data eeprom read control bit and when set high by the applic ation program will activ ate a read cycle. this bit will be automatically reset to zero by the hardware after the read cycle has fnished. setting this bit high will have no ef fect if the rden has not frst been set high. note: the wren, wr, rden and rd cannot be set high at the same time in one instruction. the wr and rd cannot be set high at the same time. rev. 1.10 ? 0 de ? e ?? e ? 1 ?? ? 01 ? rev. 1.10 ?1 de?e??e? 1?? ?01? HT45F75 body fat scale flash mcu HT45F75 body fat scale flash mcu ead ata o the m to read data from the eep rom, the read enable bit, rden , in the eec register must frs t be set high to enable the read function. the eeprom address of the data to be read must then be placed in the eea register . if the rd bit in the eec register is now set high, a read cycle will be initiated. setting the rd bit high will not initiate a read operation if the rden bit has not been set. when the read cycle term inates, the rd bit will be automatically cleared to zero, after which the data can be read from the eed register . the data will remain in the eed register until another read or write operation i s e xecuted. t he a pplication pr ogram c an po ll t he rd bi t t o de termine whe n t he da ta i s valid for reading. the eeprom address of the data to be written must frst be placed in the eea register and the data placed in the eed register . t o write data to the eeprom, the write enable bit, wren, in the eec register must frst be set high to enable the write function. after this, the wr bit in the eec register must be immediately set high to initiate a write cycle. these two instructions must be executed consecutively. the global interrupt bit emi should als o frs t be cleared before implementing any write operat ions, and then set agai n aft er the write cyc le has start ed. note that setting the wr bi t high will not initiate a write cycle if the wren bit has not been set. as the eeprom write cycle is controlled using an internal timer whose operation is asynchronous to microcontroller system clock, a certain time will elapse before the data will have been written into the eeprom. detecting when the write cycle has fnished can be implemented either by polling the wr bit in the eec register or by using the eeprom interrupt. when the write cycle terminates, the wr bit will be automatically cleared to zero by the microcontroller , informing the user that the data has been written to the eeprom. the application program can therefore poll the wr bit to determine when the write cycle has ended. protection against inadvertent write operation is provided in several ways. after the device is powered-on t he w rite e nable b it i n t he c ontrol r egister wi ll b e c leared p reventing a ny wr ite operations. also at power -on the memory pointer high byte register , mp1h or mp2h, will be reset to zero, which means that data memory sector 0 will be selected. as the eeprom control register is located in sector 1, this adds a further measure of protection against spurious write operations. during normal program operati on, ensuring that the w rite enable bit in the cont rol re gister is cleared will safeguard against incorrect write operations. the eeprom write interrupt is generated when an eeprom write cycle has ended. the eeprom interrupt must frst be enabled by setting the dee bit in the relevant interrupt register . however as the eeprom is contained within a multi-function interrupt, the associated multi-function interrupt enable bit must als o be set. when an eeprom w rite cycle ends, the d ef reques t flag and its associated multi-function interrupt request fag will both be set. if the global, eeprom and multi- function interrupts are enabled and the stack is not full, a jump to the associated multi-function interrupt vector will take place. when the interrupt is serviced only the multi-function interrupt fag will be automatically reset, the eeprom interrupt fag must be manually reset by the application program. more details can be obtained in the interrupt section. rev. 1.10 ?0 de?e??e? 1?? ?01? rev. 1.10 ? 1 de ? e ?? e ? 1 ?? ? 01 ? HT45F75 body fat scale flash mcu HT45F75 body fat scale flash mcu oa cosdeatos care must be taken that data is not inadvertently written to the eeprom. protection can be enhanced by ensuring that the w rite enable bit is normally cleared to zero when not writing. also the memory pointer high byte register , mp1h or mp2h, could be normally cleared to zero as this would inhibit access to sector 1 where the eeprom control register exist. although certainly not necessary, consideration might be given in the application program to the checking of the validity of new write data by a simple read back process. when writing data the wr bit must be set high immediately after the wren bit has been set high, to ensure the write cycle executes correctly . the global interrupt bit emi should also be cleared before a write cycle is executed and then re-enabled after the write cycle starts. note that the device should not enter the id le or sleep mode until the eeprom read or write operation is totally complete. otherwise, the eeprom read or write operation will fail. mov a, ee prom_adres ; u ser d efned ad dress mov eea, a mov a, 0 40h ; se tup m emory p ointer m p1l mov mp1l, a ; mp1 p oints t o e ec r egister mov a, 0 1h ; se tup m emory p ointer m p1h mov mp1h, a set iar1.1 ; s et r den b it, e nable r ead o perations set iar1.0 ; s tart r ead c ycle - s et r d b it back: sz iar1.0 ; c heck f or re ad c ycle e nd jmp back clr iar1 ; d isable ee prom re ad/write clr mp1h mov a, ee d ; m ove re ad d ata t o re gister mov read_data, a mov a, ee prom_adres ; u ser d efned ad dress mov eea, a mov a, e eprom_data ; u ser d efned da ta mov eed, a mov a, 0 40h ; se tup m emory p ointer m p1l mov mp1l, a ; mp1 p oints t o e ec r egister mov a, 0 1h ; se tup m emory p ointer m p1h mov mp1h, a clr emi set iar1.3 ; s et w ren b it, e nable w rite o perations set iar1.2 ; s tart w rite c ycle - s et w r b it e xecuted i mmediately ; a fter s et w ren b it set emi back: sz iar1.2 ; c heck f or wr ite c ycle e nd jmp back clr iar1 ; d isable ee prom re ad/write clr mp1h rev. 1.10 ?? de ? e ?? e ? 1 ?? ? 01 ? rev. 1.10 ?3 de?e??e? 1?? ?01? HT45F75 body fat scale flash mcu HT45F75 body fat scale flash mcu scllatos various oscillator options of fer the user a wide range of functions according to their various application requirements. the flexible features of the oscillator functions ensure that the best optimisation can be achieved in terms of speed and power saving. oscillator selections and operation are selected through a combination of confguration options and registers. in additio n to being the source of the main system clock the oscillators also provide clock sources for t he w atchdog t imer a nd t ime b ase i nterrupts. e xternal o scillators r equiring so me e xternal components as well as fully integrated internal oscillators, requiring no external components, are pr ovided t o fo rm a wi de ra nge of bo th fa st a nd sl ow syst em osc illators. al l osc illator op tions are se lected t hrough t he c onfiguration o ptions. t he hi gher fr equency o scillators pr ovide hi gher performance b ut c arry wi th i t t he d isadvantage o f h igher p ower r equirements, wh ile t he o pposite is of course true for the lower frequency osc illators. w ith the capabil ity of dynamicall y switching between fas t and s low s ystem clock, the device has the flexibility to optimize the performance/ power ratio, a feature especially important in power sensitive portable applications. exte ? nal c ? ystal hxt ? 00khz~ ? 0mhz osc1/osc ? inte ? nal high speed rc hirc ? .8 ? ? .8 ? o ? ? .83mhz exte ? nal low speed c ? ystal lxt 3 ? .7 ? 8khz xt1/xt ? inte ? nal low speed rc lirc 3 ? khz os?illato? types system clock confgurations there are four methods of generating the system clock, two high speed oscillators and two low speed oscillators. the high speed oscillators are the external crystal oscillator and the internal 4.8mhz, 4.82mhz or 4.83mhz rc oscillator . the two low speed oscillators are the internal 32khz rc oscillator and the external 32.768kh z crys tal oscillator . selecting w hether the low or high speed oscillator is us ed as the s ystem os cillator is implemented us ing the h lclk bit and ck s2~cks0 bits in the smod register and as the system clock can be dynamically selected. the actual source clock used for each of the high speed and low speed oscillators is chosen via c onfiguration opt ions. t he frequenc y of t he sl ow spe ed or hi gh spe ed syst em c lock i s a lso determined using the hlclk bit and cks2~cks0 bits in the smod register . note that two oscillator selection s must be made namely one high speed and one low speed system oscillators. it is not possible to choose a no-oscillator selection for either the high or low speed oscillator. rev. 1.10 ?? de?e??e? 1?? ?01? rev. 1.10 ? 3 de ? e ?? e ? 1 ?? ? 01 ? HT45F75 body fat scale flash mcu HT45F75 body fat scale flash mcu high speed os?illato? high speed os?illato? configu?ation option ?-stage p?es?ale? f h f h /? f h /? f h /8 f h /1? f h /3? f h /?? hlclk? cks?~cks0 ?its f sys fast wake-up f?o? sleep mode o? idle mode cont?ol (fo? hxt only) low speed os?illato? low speed os?illato? configu?ation option f sub f sub hxt hirc lirc lxt system clock confgurations the e xternal cryst al/ceramic syst em osc illator i s one of t he hi gh fre quency osc illator c hoices, which is s elected via configuration option. f or mos t crystal os cillator configurations, the s imple connection of a crystal across osc1 and osc2 will create the necessary phase shift and feedback for oscillation, without requiring extern al capacitors. however , for some crystal types and frequencies, to ensure oscillation, it may be necessary to add two small value capacitors, c1 and c2. using a ceramic resonator will usually require two small value capacitors, c1 and c2, to be connected as shown for oscillation to occur . the values of c1 and c2 should be selected in consultation with the crystal or resonator manufacturers specifcation. for oscillator stability and to minimise the ef fects of noise and crosstalk, it is important to ensure that the crystal and any associated resistors and capacitors along with interconnecting lines are all located as close to the mcu as possible. ? ? ? ? crystal/resonator oscillator ? hxt rev. 1.10 ?? de ? e ?? e ? 1 ?? ? 01 ? rev. 1.10 ?5 de?e??e? 1?? ?01? HT45F75 body fat scale flash mcu HT45F75 body fat scale flash mcu cystal scllato c ad c ales cystal feecy c c ? 0mhz 0pf 0pf 1 ? mhz 0pf 0pf 8mhz 0pf 0pf ? mhz 0pf 0pf 1mhz 100pf 100pf note: c1 and c ? values a ? e fo ? guidan ? e only. c?ystal re?o??ended capa?ito? values inte?nal rc os?illato? C hirc the internal rc oscillator is a fully integrated system oscillator requiring no external components. the inter nal rc oscillator has three fxed frequencies of either 4.8mhz, 4.82mhz or 4.83mhz. device t rimming duri ng t he m anufacturing proc ess a nd t he i nclusion of i nternal fre quency compensation circ uits are used to ensure that the infuence of the power supply voltage, temperature and process variat ions on the oscillation frequency are minimised. as a result, at a power supply of 5v and at a temperature of 25c degrees, the fxed oscillation frequency of 4.82mhz will have a tolerance within 2%. note that if this internal system clock option is selected, as it requires no external pins for its operation, i/o pins pb1 and pb2 are free for use as normal i/o pins. the internal 32khz system oscillator is one of the low frequency oscillator choices, which is selected via confguration option. it is a fully integrated rc oscillator with a typical frequency of 32khz a t 5 v, r equiring n o e xternal c omponents f or i ts i mplementation. de vice t rimming d uring the manufacturing process and the inclusion of internal frequency compensation circuits are used to ensure that the infuence of the power supply voltage, temperature and process variations on the oscillation frequency are minimised. as a result, at a power supply of 5v and at a temperature of 25c degrees, the fxed oscillation frequency of 32khz will have a tolerance within 10%. the external 32.768khz crystal system oscillator is one of the low frequency oscillator choices, which is selected via confguration option. this clock source has a fxed frequency of 32.768khz and requires a 32.768khz crystal to be connected between pins xt1 and xt2. the external resistor and capa citor components connecte d to the 32.768khz crystal are necessary to provide oscillation. for a pplications wh ere p recise f requencies a re e ssential, t hese c omponents m ay b e r equired t o provide frequency compensation due to dif ferent crystal manufacturing tolerances. during power -up there is a time delay associated with the lxt oscillator waiting for it to start-up. when the microco ntroller enters the sleep or idle mode, the system clock is switched of f to stop microcontroller a ctivity a nd t o c onserve powe r. howe ver, i n m any m icrocontroller a pplications it may be necessary to keep the internal timers operational even when the microcontroller is in the sleep or idle mode. t o do this, another clock, independent of the system clock, must be provided. however, for some crystals, to ensure oscillation and accurate frequency generation, it is necessary to add two small value external capacitors, c1 and c2. the exact values of c1 and c2 should be selected in consultation with the crystal or resonator manufacturer specification. the external parallel feedback resistor, r p , is required. rev. 1.10 ?? de?e??e? 1?? ?01? rev. 1.10 ? 5 de ? e ?? e ? 1 ?? ? 01 ? HT45F75 body fat scale flash mcu HT45F75 body fat scale flash mcu some confguration options determine if the xt1/xt2 pins are used for the lxt oscillator or as i/o pins. ? if the lxt oscillator is not used for any clock source, the xt1/xt2 pins can be used as normal i/o pins. ? if the lxt oscillator is used for any clock source, the 32.768khz crystal should be connected to the xt1/xt2 pins. for oscillator stability and to minimise the ef fects of noise and crosstalk, it is important to ensure that the crystal and any associated resistors and capacitors along with interconnecting lines are all located as close to the mcu as possible. ? ? ? ? ? ?- ? ? ? external lxt oscillator lxt oscillator c1 and c2 values crystal frequency c1 c2 3 ? .7 ? 8khz 10pf 10pf note: 1. c1 and c ? values a ? e fo ? guidan ? e only. ? . r p =5m~10m is recommended. the lxt oscillator can function in one of two modes, the quick start mode and the low power mode. the mode selection is executed using the lxtlp bit in the tbc register. 0 qui ? k sta ? t 1 low-powe ? after power on, the lxtlp bit will be automatically cleared to zero ensuring that the lxt oscillator is in the quick start operating mode. in the quick start mode the lxt oscillator will power up and stabilise quickly . however , after the lxt oscillator has fully powered up it can be placed into t he l ow-power m ode b y se tting t he l xtlp b it h igh. t he o scillator wi ll c ontinue t o r un b ut with reduced current consumption, as the higher current consumption is only required during the lxt oscillator start-up. in power sensitive applications, such as battery applications, where power consumption must be kept to a minimum, it is therefore recommended that the application program sets the lxtlp bit high about 2 seconds after power-on. it shou ld be no ted t hat, no m atter wha t c ondition t he l xtlp bi t i s se t t o, t he l xt osc illator wi ll always be function normally , the only dif ference is that it will take more time to start up if in the low-power mode. rev. 1.10 ?? de ? e ?? e ? 1 ?? ? 01 ? rev. 1.10 ?7 de?e??e? 1?? ?01? HT45F75 body fat scale flash mcu HT45F75 body fat scale flash mcu sleetay scllatos the l ow spe ed osc illators, i n a ddition t o pro viding a syst em c lock sour ce a re a lso use d t o pro vide a clock source to other device functions. these are the w atchdog t imer, the t ime base interrupts function and the sim. present day appl ications require that their mi crocontrollers have high performance but often sti ll demand that they consume as little power as possible, conficting requirements that are especially true i n ba ttery powe red por table a pplications. t he fa st c locks re quired for hi gh pe rformance wi ll by t heir na ture i ncrease c urrent c onsumption a nd of c ourse vi ce-versa, l ower spe ed c locks re duce current consumption. as holtek has provided this device with both high and low speed clock sources and the means to switch between them dynamically , the user can optimise the operation of their microcontroller to achieve the best performance/power ratio. the device has many dif ferent clock sources for both the cpu and peripheral function operation. by providing the us er w ith a w ide range of clock options us ing conf guration options and regis ter programming, a clock system can be confgured to obtain maximum application performance. the main system clock, can come from either a high frequency f h or low frequency f sub source, and is selected using the hlclk bit and cks2~cks0 bits in the smod register. the high speed system clock can be sourced from either an hxt or hirc oscillator , selected via a confguration option. the low speed system clock source can be sourced from internal clock f sub . if f sub is selected then it can be sourced by either the lxt or lirc oscillator , selected via a confguration option. the other choice, which is a divided version of the high speed system oscillator has a range of f h /2~f h /64. the f sub clock is used to provide a substitute clock for the microcontro ller just after a wake-up has occurred to enable faster wake-up times. the f sub is used as a clock source for the w atchdog timer , the t ime base interrupt, the tms and the sim functions. rev. 1.10 ?? de?e??e? 1?? ?01? rev. 1.10 ? 7 de ? e ?? e ? 1 ?? ? 01 ? HT45F75 body fat scale flash mcu HT45F75 body fat scale flash mcu high speed os?illato? high speed os?illato? configu?ation option ?-stage p?es?ale? f h f h /? f h /? f h /8 f h /1? f h /3? f h /?? hlclk? cks?~cks0 ?its f sys fast wake-up f?o? sleep mode o? idle mode cont?ol (fo? hxt only) low speed os?illato? low speed os?illato? configu?ation option f sub f sys /? tbck ti?e base f sys /? configu?ation option wdt f sub f tb f s clo?k sou??e sele?tion sim f sys f sub f sub f sub hxt hirc lirc lxt system clock confgurations note: when the system clock source f is switched to f from f , the high speed oscillation will stop to conserve the power. thus there is no f ~ /64 for peripheral circuit to use. rev. 1.10 ? 8 de ? e ?? e ? 1 ?? ? 01 ? rev. 1.10 ?9 de?e??e? 1?? ?01? HT45F75 body fat scale flash mcu HT45F75 body fat scale flash mcu syste eato modes there are six dif ferent modes of operation for the microcontroller , each one with its ow n special characteristics and which can be chosen according to the specific performance and power requirements of the appl ication. there are two modes all owing normal operati on of the microcontroller, t he normal mode a nd sl ow mode . t he re maining four m odes, t he sl eep0, sleep1, idle0 and idle1 mode are used when the microcontroller cpu is switched of f to conserve power. normal mode on f h ~f h / ?? on on slow mode on f sub on on idle0 mode off off on on/off idle1 mode off on on on sleep0 mode off off off off sleep1 mode off off on on normal mode as the name suggests this is one of the main operating modes where the microcontroller has all of its functions operational and where the system clock is provided by one of the high speed oscillators. this mode operate s allowing the microcontroller to operate normally with a clock source will come from one of the high speed oscillators, either the hxt or hirc oscillators. the high speed oscillator will however frst be divided by a ratio ranging from 1 to 64, the actual ratio being selected by the cks2~cks0 and hlclk bits in the smod register . although a high speed oscillator is used, running the microcontroller at a divided clock ratio reduces the operating current. this is also a mode where the microcontroller operates normally altho ugh now with a slower speed clock source. the clock source used will be from one of the low speed oscillators, either the lxt or the lirc. running the microcontroller in this mode allows it to run with much lower operating currents. in the slow mode, the f h is off. the sleep mode is entered when an hal t instruction is executed and when the idlen bit in the smod register is low . in the sleep0 mode the cpu will be stopped, and the f sub and f s clocks will be stopped too, and the w atchdog t imer function is disabled. in this mode, the l vden is must cleared to zero. if the lvden is set high, it wont enter the sleep0 mode. the s leep m ode is entered w hen an h alt instruction is executed and w hen the id len bit in the smod register is low . in the sleep1 mode the cpu will be stopped. however the f sub and f s clocks will continue to operate if the l vden is 1 or the w atchdog t imer function is enabled and if its clock source is chosen via confguration option to come from the f sub . the idle0 mode is entered when a hal t instruction is executed and when the idlen bit in the smod regi ster i s high and t he fsyson bit i n t he ctrl regi ster i s l ow. in t he idle 0 mode t he system oscillator will be inhibited from driving the cpu but some peripheral functions will remain operational such as the w atchdog t imer, tms and sim. in the idle0 mode, the system oscillator will be stopped. in the idle0 mode the w atchdog t imer clock, f s , will either be on or off depending rev. 1.10 ?8 de?e??e? 1?? ?01? rev. 1.10 ? 9 de ? e ?? e ? 1 ?? ? 01 ? HT45F75 body fat scale flash mcu HT45F75 body fat scale flash mcu upon the f clock source. if the source is f /4 then the f s clock will be of f, and if the source comes from f then f will be on. idle1 mode the idle1 mode is entered when an ha lt ins truction is executed and when the idlen bit in the smod register is high and the fsyson bit in the ctrl register is high. in the idle1 mode the syst em osc illator wil l be i nhibited from dri ving t he cpu but m ay c ontinue t o provi de a c lock source to keep some peripheral functions operational such as the w atchdog t imer, tms and sim. in the idle1 mode, the system oscillator will continue to run, and this system oscillator may be high speed or low speed system oscillato r. in the idle1 mode the w atchdog t imer clock, f , will be on. if the source is f /4 then the f clock will be on, and if the source comes from f then f will be on. control register the registers, smod and ctrl, are used for overall control of the internal clocks within the device. smod register bit 7 6 5 4 3 2 1 0 na ? e cks ? cks1 cks0 fsten lto hto idlen hlclk r/w r/w r/w r/w r/w r r r/w r/w por 0 0 0 0 0 0 1 1 bit 7~5 : the system clock selection when hlclk is 0 000: f (f lxt or f lirc ) 001: f (f lxt or f lirc ) 010: f /64 011: f /32 100: f /16 101: f /8 110: f /4 111: f /2 these three bits are used to select which clock is used as the system clock source. in addition to the system clock source, which can be either the lxt or lirc, a divided version of the high speed system oscillator can also be chos en as the system clock source. bit 4 : fast w ake-up control (only for hxt) 0: disable 1: enable this is the fast w ake-up control bit which determines if the f clock source is initially used after the device wakes up. when the bit is high, the f clock source can be used as a tempo rary system clock to provide a faster wake up time as the f clock is available. bit 3 : low speed system oscillator ready fag 0: not ready 1: ready this is the low speed system oscillator ready fag which indicates when the low speed system oscillator is stable after power on reset or a wake-up has occurred. the fag will be low when in the sleep0 mode but after a wake-up has occurred, the fag will change t o a hi gh l evel a fter 10 24 c lock c ycles i f t he l xt osc illator i s use d a nd 1~ 2 clock cycles if the lirc oscillator is used. rev. 1.10 50 de ? e ?? e ? 1 ?? ? 01 ? rev. 1.10 51 de?e??e? 1?? ?01? HT45F75 body fat scale flash mcu HT45F75 body fat scale flash mcu bit 2 : high speed system oscillator ready fag 0: not ready 1: ready this is the high speed system oscillator ready fag which indicates when the high speed system oscillator is stable. this fag is cleared to zero by hardware when the device is powered on and then changes to a high level after the high speed system oscillator is stable. therefore this fag will always be read as "1" by the application program after device power-on. the fag will be low when in the sleep or idle0 mode but after a wake- up has occurred, the fag will change to a high level after 1024 clock cycles if the hxt oscillator is used and after 15~16 clock cycles if the hirc oscillator is used. bit 1 : idle mode control 0: disable 1: enable this is the idle mode control bit and determines what happens when the hal t instruction is executed. if this bit is high, when a hal t instruction is executed the device wi ll e nter t he i dle mo de. i n t he i dle1 mo de t he c pu wi ll st op r unning but t he syst em c lock wi ll c ontinue t o ke ep t he pe ripheral fun ctions op erational, i f fsyson bit is high. if fsyson bit is low, the cpu and the system clock will all stop in idle0 mode. if the bit is low the device will enter the sleep mode when a hal t instruction is executed. bit 0 : system clock selection 0: f h /2 ~ f h /64 or f sub 1: f h this bit is used to select if the f h clock or the f h /2~f h /64 or f sub clock is used as the system clock. when the bit is high the f h clock will be selected and if low the f h /2~f h /64 or f sub clock will be selected. when system clock sw itches from the f h clock to the f sub clock and the f h clock will be automatically switched of f to conserve power. na ? e fsyson lvrf lrf wrf r/w r/w r/w r/w r/w por 0 x 0 0 x unknown bit 7 : f sys control in idle mode 0: disable 1: enable bit 6~3 unimplemented, read as "0" bit 2 : lvr function reset fag described elsewhere. bit 1 : lvr control register software reset fag described elsewhere. bit 0 : wdt control register software reset fag described elsewhere. rev. 1.10 50 de?e??e? 1?? ?01? rev. 1.10 51 de ? e ?? e ? 1 ?? ? 01 ? HT45F75 body fat scale flash mcu HT45F75 body fat scale flash mcu fast ae to minimise power consumption the device can enter the sleep or idle0 mode, where the system clock source to the device will be stopped. however when the device is woken up again, it can take a considerable time for the original system oscillator to restart, stabilise and allow normal operation to re sume. t o e nsure t he de vice i s up a nd runni ng a s fa st a s possi ble a fa st w ake-up func tion i s provided, which allows f sub , namel y either the lxt or lirc oscillator , to act as a temporary clock to frst drive the system until the original system oscillator has stabilised. as the clock source for the fast w ake-up function is f sub , the fast w ake-up function is only available in the sleep1 and idle0 modes. when the device is woken up from the sleep0 mode, the fast w ake-up function has no ef fect because the f sub clock is stopped. the fast w ake-up enable/ disable function is controlled using the fsten bit in the smod register. if the hxt oscil lator is sel ected as the normal mode syste m cl ock, and if the fa st w ake-up function is enabled, then it will take one to two t sub clock cycles of the lirc or lxt oscillator for the system to wake-up. the system will then initially run under the f sub clock source until 1024 hxt clock cycles have elapsed, at which point the ht o fag will switch high and the system will switch over to operating from the hxt oscillator. if the hirc oscillator or lirc oscillator is used as the system oscillator then it will take 15~16 clock c ycles of t he hirc or 1~2 c ycles of t he l irc t o wa ke up t he syst em from t he sl eep or idle0 mode. the fast w ake-up bit, fsten will have no effect in these cases. (sleep0 mode) (sleep1 mode) (idle0 mode) (idle1 mode) hxt 0 10 ?? hxt ? y ? les 10 ?? hxt ? y ? les 1~ ? hxt ? y ? les 1 10 ?? hxt ? y ? les 1~ ? f sub ? y ? les (syste ? ? uns with f sub uvwiru+;7 ? y ? les and then swit ? hes ove ? to ? un with the hxt ? lo ? k) 1~ ? hxt ? y ? les hirc x 15~1 ? hirc ? y ? les 15~1 ? hirc ? y ? les 1~ ? hirc ? y ? les lirc x 1~ ? lirc ? y ? les 1~ ? lirc ? y ? les 1~ ? lirc ? y ? les lxt x 10 ?? lxt ? y ? les 10 ?? lxt ? y ? les 1~ ? lxt ? y ? les x: dont ? a ? e wake-up ti?es note that if the w atchdog t imer is disabled, which means that the lxt and lirc are all both of f, then there will be no fast w ake-up function available when the device wake-up from the sleep0 mode. the devi ce c an swi tch bet ween opera ting m odes dynam ically a llowing t he use r t o se lect t he best performance/power ratio for the pres ent task in hand. in this w ay microcontroller operations that do not require high performance can be executed using slower clocks thus requiring less operating current and prolonging battery life in portable applications. in simple terms, mode switching between the normal mode and slow mode is executed using the hlclk bit and cks2~cks0 bits in the smod register while mode switching from the normal/slow modes to the sleep/idle modes is executed via the hal t instruction. when a hal t instructio n is executed, whether the device enters the idle mode or the sleep mode is determined by the condit ion of the idl en bit in the smod regi ster and fsyson in the ctrl register. rev. 1.10 5 ? de ? e ?? e ? 1 ?? ? 01 ? rev. 1.10 53 de?e??e? 1?? ?01? HT45F75 body fat scale flash mcu HT45F75 body fat scale flash mcu when the hlclk bit switches to a low level, which implies that clock source is switched from the high speed clock source, f , to the clock source, f /2~f /64 or f . if the clock is from the f , the high speed clock source will stop running to conserve power . when this happens it must be noted that the f /16 and f /64 internal cloc k sources will also stop running, which may af fect the operation of other internal functions such as the tms and the sim. the accompanying fowchart shows what happens when the device moves between the various operating modes. ? ? ?? ? ? - ? ? ? - ? ? rev. 1.10 5? de?e??e? 1?? ?01? rev. 1.10 53 de ? e ?? e ? 1 ?? ? 01 ? HT45F75 body fat scale flash mcu HT45F75 body fat scale flash mcu m mode to s mode stch when r unning i n t he nor mal mo de, wh ich u ses t he h igh sp eed sy stem o scillator, a nd t herefore consumes more power, the system clock can switch to run in the slow mode by set the hlclk bit to 0 and set the cks2~cks0 bits to 000 or 001 in the smod register . this will then use the low speed system oscillator which will consume less power . users may decide to do this for certain operations which do not require high performance and can subsequently reduce power consumption. the sl ow mode is sourc ed from the lxt or the lirc osci llators and therefore requi res these oscillators to be stable before full mode switching occurs. this is monitored using the l to bit in the smod register. ? ? ? ? ? ? ? ?- ?? ?? -? ? ? ? ? ? ? ?- ?? ?? -? ? ? ? ? ? ? ? ?- ?? ? ? -?? ? ? ? ? ? ? ?- ?? ?? -? ? rev. 1.10 5 ? de ? e ?? e ? 1 ?? ? 01 ? rev. 1.10 55 de?e??e? 1?? ?01? HT45F75 body fat scale flash mcu HT45F75 body fat scale flash mcu s mode to m mode stch in slow mode the system uses either the lxt or lirc low speed system oscillator . t o switch back to the normal mode, where the high speed system oscillator is used, the hlclk bit should be set high or hlclk bit is 0, but cks2~cks0 is set to 010, 01 1, 100, 101, 1 10 or 111. as a c ertain a mount of t ime wi ll be re quired for t he hi gh fre quency c lock t o sta bilise, t he status of the ht o bit is checked. the amount of time required for high speed system oscillator stabilization depends upon which high speed system oscillator type is used. ? ? ? ? ? ? ?? ?? ? - ?? ? ? ? ? ?? ?? ? - ?? ? ? ? ? ? ?? ?? ? -??? ? ? ? ? ?? ?? ? - ?? ? entering the sleep0 mode there is only one way for the devic e to enter the sleep0 mode and that is to execute the hal t instruction i n t he a pplication p rogram wi th t he i dlen b it i n smod r egister e qual t o 0 a nd t he wdt and l vd both of f. when this instruction is executed under the conditions described above, the following will occur: ? the system clock and the f sub clock will be stopped and the appli cation program will stop at the halt instruction. ? the data memory contents and registers will maintain their present condition. ? the wdt will be cleared and stopped no matter if the wdt clock source originates from the f sub clock or from the system clock. ? the i/o ports will maintain their present conditions. ? in the status register , the power down fag, pdf , will be set and the w atchdog time-out fag, t o, will be cleared. rev. 1.10 5? de?e??e? 1?? ?01? rev. 1.10 55 de ? e ?? e ? 1 ?? ? 01 ? HT45F75 body fat scale flash mcu HT45F75 body fat scale flash mcu te the s mode there is only one way for the devic e to enter the sleep1 mode and that is to execute the hal t instruction i n t he a pplication p rogram wi th t he i dlen b it i n smod r egister e qual t o 0 a nd t he wdt or l vd on. w hen t his i nstruction i s e xecuted unde r t he c onditions de scribed a bove, t he following will occur: ? the system clock will be stopped and the application program will stop at the hal t instruction, but the wdt or lvd will remain with the clock source coming from the f sub clock. ? the data memory contents and registers will maintain their present condition. ? the wdt will be cleared and resume counting if the wdt clock source is selected to come from the f sub clock as the wdt is enabled. ? the i/o ports will maintain their present conditions. ? in the status register , the power down fag, pdf , will be set and the w atchdog time-out fag, t o, will be cleared. there is only one way for the device to enter the idle0 mode and that is to execute the hal t instruction i n t he a pplication p rogram wi th t he i dlen b it i n smod r egister e qual t o 1 a nd t he fsyson bit in ctrl register equal to 0. when this instruction is executed under the conditions described above, the following will occur: ? the system clock will be stopped and the application program will stop at the hal t instruction, but the f sub clock will be on. ? the data memory contents and registers will maintain their present condition. ? the wdt will be cleared and resume counting if the wdt clock source is selected to come from the f sub clock and the wdt is enabled. the wdt will stop if its clock source originates from the system clock. ? the i/o ports will maintain their present conditions. ? in the status register , the power down fag, pdf , will be set and the w atchdog time-out fag, t o, will be cleared. there is only one way for the device to enter the idle1 mode and that is to execute the hal t instruction i n t he a pplication p rogram wi th t he i dlen b it i n smod r egister e qual t o 1 a nd t he fsyson bit in ctrl register equal to 1. when this instruction is executed under the conditions described above, the following will occur: ? the system clock and the f sub clock will be on and the application program will stop at the halt instruction. ? the data memory contents and registers will maintain their present condition. ? the wdt wil l be cle ared and resume count ing if the wdt is enabled rega rdless of the wdt clock source which originates from the f sub clock or from the system clock. ? the i/o ports will maintain their present conditions. ? in the status register , the power down fag, pdf , will be set and the w atchdog time-out fag, t o, will be cleared. rev. 1.10 5 ? de ? e ?? e ? 1 ?? ? 01 ? rev. 1.10 57 de?e??e? 1?? ?01? HT45F75 body fat scale flash mcu HT45F75 body fat scale flash mcu stady cet cosdeatos as the main reason for entering the sleep or idle mode is to keep the current consumption of the device to as low a value as possible, perhaps only in the order of several micro-amps except in the idle1 mode , t here a re ot her c onsiderations whi ch m ust a lso be t aken i nto a ccount by t he c ircuit designer if the power consumption is to be minimised. special attention must be made to the i/o pins on the device. all high-impedance input pins must be connected to either a fxed high or low level as any foating input pins could create internal oscillations and result in increased current consumption. this also applies to the device which has dif ferent package types, as there may be unbonbed pins. these must either be setup as outputs or if setup as inputs must have pull-high resistors connected. care must also be taken with the loads, which are connected to i/o pins, which are setup as outputs. these should be placed in a condition in which minimum current is drawn or connected only to external circuits that do not draw current, such as other cmos inputs. also note that additional standby current will also be required if the confguration options have enabled the lxt or lirc oscillator. in the idle1 mode the system oscillator is on, if the system oscillator is from the high speed system oscillator, the additional standby current will also be perhaps in the order of several hundred micro- amps. after the system enters the sleep or idle mode, it can be woken up from one of various sources listed as follows: ? an external falling edge on port a ? a system interrupt ? a wdt overfow if the device is woken up by a wdt overfow , a w atchdog t imer reset will be initiated. the pdf fag is cleared by a system power -up or executing the clear w atchdog t imer instructions and is set when executing the hal t instruction. the t o fag is set if a wdt time-out occurs, and causes a wake-up that only resets the program counter and stack pointer , the other fags remain in their original status. each pin on port a can be setup using the p awu register to permit a negative transition on the pin to wake-up t he syste m. when a port a pin wake-up occurs, the progra m wil l resume exec ution at the i nstruction f ollowing t he halt i nstruction. i f t he sy stem i s wo ken u p by a n i nterrupt, t hen two possible situations may occur . the frst is where the related interrupt is disabled or the interrupt is enabled but the stack is full, in which case the program will resume execution at the instruction following the hal t instruction. in this situation, the interrupt which woke-up the device will not be immediately serviced, but will rather be serviced later when the related interrupt is fnally enabled or when a stack level becomes free. the other situation is where the related interrupt is enabled and the stack is not full, in which case the regular interrupt response takes place. if an interrupt request flag i s se t hi gh be fore e ntering t he sle ep or idl e mode, t he wa ke-up func tion of t he re lated interrupt will be disabled. rev. 1.10 5? de?e??e? 1?? ?01? rev. 1.10 57 de ? e ?? e ? 1 ?? ? 01 ? HT45F75 body fat scale flash mcu HT45F75 body fat scale flash mcu oa cosdeatos the hxt and lxt oscillators both use the same sst counter . for example, if the system is woken up from the sleep0 mode and both the hxt and lxt oscillators need to start-up from an of f state. the lxt oscillator uses the sst counter after hxt oscillator has fnished its sst period. ? if the device is woken up from the sleep0 mode to the normal mode, the high speed system oscillator needs an sst period. the device will execute frst instruction after ht o is 1. at this time, t he l xt o scillator m ay n ot b e st ability i f f sub i s f rom l xt o scillator. t he sa me si tuation occurs in the power -on state. the lxt oscillator is not ready yet when the frst instruction is executed. ? if the device is woken up from the sleep1 mode to normal mode, and the system clock source is from hxt oscillator and fsten is 1, the system clock can be switched to the lxt or lirc oscillator after wake up. ? there are peripheral functions, such as wdt , tms and sim, for which the f sys is used. if the system clock source is switched from f h to f sub , the clock source to the peripheral functions mentioned above will change accordingly. the w atchdog t imer is provided to prevent program malfunctions or sequences from jumping to unknown locations, due to certain uncontrollable external events such as electrical noise. the w atchdog t imer clock source is provided by the internal clock, f s , which is in turn supplied by one of two sources selected by confguration option: f sub or f sys /4. the f sub clock can be sourced from either the lx t or lirc oscillators , again chosen via a confguration option. the w atchdog timer source clock is then subdivided by a ratio of 2 8 to 2 18 to give longer timeouts, the actual value being chosen using the ws2~ws0 bits in the wdtc register . the lirc internal oscillator has an approximate period of 32khz at a supply voltage of 5v . however , it should be noted that this specified internal clock period can vary with v dd , temperature and process variations. the lxt oscillator is supplied by an external 32.768khz crystal. the other w atchdog t imer clock source option is the f sys /4 clock. a single register , wdtc, controls the required timeout period as well as the enable/disable operation. this register together with several confguration options control the overall operation of the w atchdog t imer. rev. 1.10 58 de ? e ?? e ? 1 ?? ? 01 ? rev. 1.10 59 de?e??e? 1?? ?01? HT45F75 body fat scale flash mcu HT45F75 body fat scale flash mcu tc este bt 7 5 4 na ? e we ? we3 we ? we1 we0 ws ? ws1 ws0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 1 0 1 0 0 1 1 bit 7~3 we4~we0 : wdt function software control if the wdt confguration option is always enable: 10101 or 01010: enable others: reset mcu if the wdt confguration option is controlled by the wdt control register: 10101: disable 01010: enable others: reset mcu when these bits are changed by the environmental noise or software setting to reset the m icrocontroller, t he re set ope ration wi ll be a ctivated a fter 2~3 f c lock c ycles and the wrf bit in the ctrl register will be set high. bit 2~0 ws2~ws0 : wdt time-out period selection 000: 2 /f 001: 2 10 /f 010: 2 12 /f 011: 2 14 /f 100: 2 15 /f 101: 2 16 /f 110: 2 17 /f 111: 2 /f na ? e fsyson lvrf lrf wrf r/w r/w r/w r/w r/w por 0 x 0 0 x unknown bit 7 fsyson : f control in idle mode described elsewhere. bit 6~3 unimplemented, read as 0 bit 2 lvrf : lvr function reset fag described elsewhere. bit 1 lrf : lvr control register software reset fag described elsewhere. bit 0 wrf : wdt control register software reset fag 0: not occur 1: occurred this bit is set high by the wdt control register software reset and cleared by the application program. note that this bit can only be cleared to zero by the application program. rev. 1.10 58 de?e??e? 1?? ?01? rev. 1.10 59 de ? e ?? e ? 1 ?? ? 01 ? HT45F75 body fat scale flash mcu HT45F75 body fat scale flash mcu atchdo te eato the w atchdog t imer ope rates by provi ding a de vice re set whe n i ts t imer ove rfows. t his m eans that i n t he a pplication pro gram a nd dur ing nor mal ope ration t he use r ha s t o st rategically c lear t he watchdog t imer before it overfows to prevent the w atchdog t imer from executing a reset. this is done using the cle ar watchdog instructions. if the program malfunction s for whatever reason, jumps to an unknown location, or enters an endless loop, these clear instructions will not be executed in the correct manner , in which case the w atchdog t imer will overfow and reset the device. some of the watchdog t imer options, such as always on select using confguration options. w ith regard to the watchdog t imer enable/disable function, there are also fve bits, we4~we0, in the wdtc register to of fer additional enable/disable and reset control of the w atchdog t imer. if the wdt confguration option is determined that the wdt function is always enabled, the we4~we0 bits still have effects on the wdt function. when the we4~we0 bits value is equal to 01010b or 10101b, the wdt function is enabled. however , if the we4~we0 bits are change d to any other values except 01010b and 10101b, w hich is caus ed by the environmental nois e or s oftware s etting, it w ill res et the micro controller after 2~3 f sub clock cycles. if the wdt confguration option is determined that the wdt function is controlled by the wdt control register , the we4~we0 values can determine which mode the wdt operates in. the wdt function will be disabled when the we4~we0 bits are set to a value of 10101b. the wdt function will be enabled if the we4~we0 bits value is equal to 01010b. if the we4~we0 bits are set to any other values by the environmental noise or software setting, except 01010b and 10101b, it will reset the device after 2~3 f sub clock cycles. after power on these bits will have the value of 01010b. wdt confguration option always ena ? le 01010b o ? 10101b ena ? le any othe ? values reset mcu cont ? olled ? y wdt cont ? ol registe ? 10101b disa ? le 01010b ena ? le any othe ? values reset mcu wat?hdog ti?e? ena?le/disa?le cont?ol under norm al progra m ope ration, a w atchdog t imer t ime-out wi ll i nitialise a de vice re set a nd se t the status bit t o. however , if the system is in the sleep or idle mode, when a w atchdog t imer time-out occurs, the t o bit in the status register will be set and only the program counter and stack pointer will be reset. three methods can be adopted to clear the contents of the w atchdog t imer. the frst is a wdt reset, which means a certain value except 01010b and 10101b written into the we4~we0 bit fled, the second is using the w atchdog t imer software clear instructions and the third is via a halt instruction. there is only one method of using software instruction to clear the w atchdog t imer. that is to use the single clr wdt instruction to clear the wdt . the maximum time out period is when the 2 18 division ratio is selected. as an example, with a 32khz lirc oscillator as its source clock, this will give a maximum watchdog period of around 8 second for the 2 18 division ratio, and a minimum timeout of 7.8ms for the 2 8 division ration. rev. 1.10 ? 0 de ? e ?? e ? 1 ?? ? 01 ? rev. 1.10 ?1 de?e??e? 1?? ?01? HT45F75 body fat scale flash mcu HT45F75 body fat scale flash mcu clr wdt inst?u?tion we?~we0 ?its wdtc registe? reset mcu f s clr halt inst?u?tion f sub m u x configu?ation option m u x f sys /? lxt lirc configu?ation option 8-stage divide? wdt p?es?ale? f s /? 8 8-to-1 mux ws?~ws0 wdt ti?e-out wat?hdog ti?e? reset and initialisation a reset function is a fundamental part of any microcontroller ensuring that the device can be set to some predetermined condition irrespective of outside parameters. the most important reset condition is after power is frst applied to the microcontroller . in this case, internal circuitry will ensure that the mi crocontroller, after a short delay , wil l be in a well -defined stat e and ready to execute t he fr st p rogram i nstruction. af ter t his p ower-on r eset, c ertain i mportant i nternal r egisters will be set to defned states before the program commences. one of these registers is the program counter, which will be reset to zero forcing the microcontroller to begin program execution from the lowest program memory address. another type of reset is when the w atchdog t imer overfows and resets. all types of reset operations result in dif ferent register condition s being setup. another reset exists in the form of a low v oltage reset, l vr, where a ful l re set, i s i mplemented i n sit uations where t he power suppl y vol tage fa lls below a certain threshold. there are several ways in which a reset can occur, each of which will be described as follows. the m ost fund amental a nd una voidable re set i s t he one t hat oc curs a fter powe r i s frst a pplied t o the microcontroller . as well as ensuring that the program memory begins execution from the frst memory address, a pow er-on reset als o ensures that certain other registers are preset to known conditions. all the i/o port and port control registers will power up in a high condition ensuring that all i/o ports will be frst set to inputs. vdd powe?-on reset sst ti?e-out t rstd note: t rstd is power-on delay, typical time=50ms rev. 1.10 ?0 de?e??e? 1?? ?01? rev. 1.10 ? 1 de ? e ?? e ? 1 ?? ? 01 ? HT45F75 body fat scale flash mcu HT45F75 body fat scale flash mcu o oltae eset the micr ocontroller contains a low voltage reset circuit in order to monitor the supply voltage of the device. the l vr function is always enabled with a specifc l vr voltag e v lvr . if the supply voltage of the device drops to within a range of 0.9v~v lvr such as might occur when changing the battery , the l vr will automatically reset the device internally and the l vrf bit in the ctrl register will also be set high. for a valid l vr signal, a low supply voltage, i.e., a voltage in the range between 0.9v~v lvr must exist for a time greater than that specifed by t lvr in the a.c. characteristics. if the low supply voltag e state does not exceed this value, the l vr will ignore the low supply voltage and will not perform a reset function. the actual v lvr value can be selected by the l vs7~lvs0 bits in the l vrc register . if the l vs7~lvs0 bits are changed to some certain values by the environmental noise or software setting, the l vr will reset the device after 2~3 f sub clock cycles. when this happens, the lrf bit in the ctrl register will be set high. after power on the register will have the value of 01010101b. note that the l vr function will be automatically disabled when the device enters the power down mode. note: t rstd is power-on delay, typical time=16.7ms ? na ? e lvs7 lvs ? lvs5 lvs ? lvs3 lvs ? lvs1 lvs0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 1 0 1 0 1 0 1 bit 7~0 : lvr voltage select 01010101: 2.1v 00110011: 2.55v 10011001: 3.15v 10101010: 3.8v other values: mcu reset (register is reset to por value). when an actual low voltage condit ion occurs, as specifed by one of the four defned lvr voltage values above, an mcu reset will be generated. the reset operation will be activated after 2~3 f sub clock cycles. in this situation the register content s will remain the same after such a reset occurs. any register value, other than the four defned l vr values above, will also result in the generation of an mcu reset. the reset operation will be activated after 2~3 f sub clock cycles. however in this situation the register contents will be reset to the por value. rev. 1.10 ?? de ? e ?? e ? 1 ?? ? 01 ? rev. 1.10 ?3 de?e??e? 1?? ?01? HT45F75 body fat scale flash mcu HT45F75 body fat scale flash mcu ? na ? e fsyson lvrf lrf wrf r/w r/w r/w r/w r/w por 0 x 0 0 x unknown bit 7 fsyson : f control in idle mode described elsewhere. bit 6~3 unimplemented, read as 0 bit 2 lvrf : lvr function reset fag 0: not occur 1: occurred this bit is set high when a specifc low v oltage reset situation condition occurs. this bit can only be cleared to zero by the application program. bit 1 lrf : lvr control register software reset fag 0: not occur 1: occurred this bit is set high if the l vrc register contains any non-defned l vr voltage register values. this in ef fect acts like a software reset function. this bit can only be cleared to zero by the application program. bit 0 wrf : wdt control register software reset fag described elsewhere. the w atchdog time-out reset during normal operation is the same as l vr reset except that the watchdog time-out fag t o will be set high. note: t rstd is power-on delay, typical time=16.7ms the w atchdog time-out reset during sleep or idle mode is a little dif ferent from other kinds of re set. mo st of t he c onditions re main unc hanged e xcept t hat t he pro gram count er a nd t he st ack pointer will be cleared to zero and the t o fag will be set high. refer to the a.c. characteristics for sst details. note: the t sst is 15~16 clock cycles if the system clock source is provided by hirc. the t sst is 1024 clock for hxt or lxt. the t sst is 1~2 clock for lirc. rev. 1.10 ?? de?e??e? 1?? ?01? rev. 1.10 ? 3 de ? e ?? e ? 1 ?? ? 01 ? HT45F75 body fat scale flash mcu HT45F75 body fat scale flash mcu eset tal codtos the dif ferent types of reset described af fect the reset fags in dif ferent ways. these fags, known as p df and t o are located in the s tatus regis ter and are controlled by various microcontroller operations, su ch a s t he sl eep o r i dle mo de f unction o r w atchdog t imer. t he r eset f lags a re shown in the table: 0 0 powe ? -on ? eset u u lvr ? eset du ? ing no ?? al o ? slow mode ope ? ation 1 u wdt ti ? e-out ? eset du ? ing no ?? al o ? slow mode ope ? ation 1 1 wdt ti ? e-out ? eset du ? ing idle o ? sleep mode ope ? ation note: u stands fo ? un ? hanged the following table indicates the way in which the various components of the microcontroller are affected after a power-on reset occurs. p ? og ? a ? counte ? reset to ze ? o inte ?? upts all inte ?? upts will ? e disa ? led wdt clea ? afte ? ? eset ? wdt ? egins ? ounting ti ? e ? modules ti ? e ? modules will ? e tu ? ned off input/output po ? ts i/o po ? ts will ? e setup as inputs ? and an0~an3 as a/d input pin. sta ? k pointe ? sta ? k pointe ? will point to the top of the sta ? k the dif ferent kinds of resets all af fect the internal registers of the micr ocontroller in dif ferent ways. to ensure reliable continuation of normal program execution after a reset occurs, it is important to know what condition the microcontroller is in after a particular reset occurs. the following table describes how each type of reset affects each of the microcontroller internal registers. (normal operation) (normal operation) (halt) mp0 0000 0000 0000 0000 0000 0000 uuuu uuuu mp1l 0000 0000 0000 0000 0000 0000 uuuu uuuu mp1h 0000 0000 0000 0000 0000 0000 uuuu uuuu mp ? l 0000 0000 0000 0000 0000 0000 uuuu uuuu mp ? h 0000 0000 0000 0000 0000 0000 uuuu uuuu iar0 xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu iar1 xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu iar ? xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu acc xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu pcl 0000 0000 0000 0000 0000 0000 0000 0000 tblp xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu tblh xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu tbhp ---- xxxx ---- uuuu ---- uuuu ---- uuuu status xx00 xxxx xxuu uuuu xx1u uuuu xx11 uuuu smod 0000 0011 0000 0011 0000 0011 uuuu uuuu integ ---- 0000 ---- 0000 ---- 0000 ---- uuuu lvdc --00 -000 --00 -000 --00 -000 --uu uuu intc0 -000 0000 -000 0000 -000 0000 -uuu uuuu intc1 0000 0000 0000 0000 0000 0000 uuuu uuuu intc ? --00 --00 --00 --00 --00 --00 --uu uu mfi0 --00 --00 --00 --00 --00 --00 --uu uu mfi1 0000 0000 0000 0000 0000 0000 uuuu uuuu rev. 1.10 ?? de ? e ?? e ? 1 ?? ? 01 ? rev. 1.10 ?5 de?e??e? 1?? ?01? HT45F75 body fat scale flash mcu HT45F75 body fat scale flash mcu este oe eset eset (normal operation) (normal operation) (halt) mfi ? 0-00 0-00 0-00 0-00 0-00 0-00 u-uu u-uu mfi3 --00 --00 --00 --00 --00 --00 --uu uu pa 1111 1111 1111 1111 1111 1111 uuuu uuuu pac 1111 1111 1111 1111 1111 1111 uuuu uuuu pb 1111 1111 1111 1111 1111 1111 uuuu uuuu pbc 1111 1111 1111 1111 1111 1111 uuuu uuuu pc 1111 1111 1111 1111 1111 1111 uuuu uuuu pcc 1111 1111 1111 1111 1111 1111 uuuu uuuu pd ---- -111 ---- -111 ---- -111 ---- -uuu pdc ---- -111 ---- -111 ---- -111 ---- -uuu wdtc 0101 0011 0101 0011 0101 0011 uuuu uuuu tbc 0011 0111 0011 0111 0011 0111 uuuu uuuu pawu 0000 0000 0000 0000 0000 0000 uuuu uuuu papu 0000 0000 0000 0000 0000 0000 uuuu uuuu pbpu 0000 0000 0000 0000 0000 0000 uuuu uuuu pcpu 0000 0000 0000 0000 0000 0000 uuuu uuuu pdpu ---- -000 ---- -000 ---- -000 ---- -uuu tm0c0 0000 0000 0000 0000 0000 0000 uuuu uuuu tm0c1 0000 0000 0000 0000 0000 0000 uuuu uuuu tm0dl 0000 0000 0000 0000 0000 0000 uuuu uuuu tm0dh ---- --00 ---- --00 ---- --00 ---- --uu tm0al 0000 0000 0000 0000 0000 0000 uuuu uuuu tm0ah ---- --00 ---- --00 ---- --00 ---- --uu sledc0 0000 0000 0000 0000 0000 0000 uuuu uuuu sledc1 --00 0000 --00 0000 --00 0000 --uu uuuu pwrc 00-- -000 00-- -000 00-- -000 uu-- -uuu pgac0 -000 0000 -000 0000 -000 0000 -uuu uuuu pgac1 10-- 000- 10-- 000- 10-- 000- uu-- uuu- pgacs --00 0000 --00 0000 --00 0000 --uu uuuu usr 0000 1011 0000 1011 0000 1011 uuuu uuuu ucr1 0000 00x0 0000 00x0 0000 00x0 uuuu uuuu ucr ? 0000 0000 0000 0000 0000 0000 uuuu uuuu brg xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu txrrxr xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu irctrl0 0000 0000 0000 0000 0000 0000 uuuu uuuu irctrl1 ---- ---0 ---- ---0 ---- ---0 ---- ---u adcr0 0010 00-0 0010 00-0 0010 00-0 uuuu uu-u adcr1 0000 000- 0000 000- 0000 000- uuuu uuu- adrl xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu adrh ---- xxxx ---- xxxx ---- xxxx ---- uuuu adcs ---0 0000 ---0 0000 ---0 0000 ---u uuuu adrm xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu lvrc 0101 0101 0101 0101 0101 0101 uuuu uuuu ctrl 0--- -x00 0--- -x00 0--- -x00 u--- -uuu ptm1c0 0000 0--- 0000 0--- 0000 0--- uuuu u--- ptm1c1 0000 0000 0000 0000 0000 0000 uuuu uuuu ptm1dl 0000 0000 0000 0000 0000 0000 uuuu uuuu rev. 1.10 ?? de?e??e? 1?? ?01? rev. 1.10 ? 5 de ? e ?? e ? 1 ?? ? 01 ? HT45F75 body fat scale flash mcu HT45F75 body fat scale flash mcu este oe eset eset (normal operation) (normal operation) (halt) ptm1dh ---- --00 ---- --00 ---- --00 ---- --uu ptm1al 0000 0000 0000 0000 0000 0000 uuuu uuuu ptm1ah ---- --00 ---- --00 ---- --00 ---- --uu ptm ? c0 0000 0--- 0000 0--- 0000 0--- uuuu u--- ptm ? c1 0000 0000 0000 0000 0000 0000 uuuu uuuu ptm ? dl 0000 0000 0000 0000 0000 0000 uuuu uuuu ptm ? dh ---- --00 ---- --00 ---- --00 ---- --uu ptm ? al 0000 0000 0000 0000 0000 0000 uuuu uuuu ptm ? ah ---- --00 ---- --00 ---- --00 ---- --uu ctrl0 ---- -000 ---- -000 ---- -000 ---- -uuu ptm1rpl 0000 0000 0000 0000 0000 0000 uuuu uuuu ptm1rph ---- --00 ---- --00 ---- --00 ---- --uu ptm ? rpl 0000 0000 0000 0000 0000 0000 uuuu uuuu ptm ? rph ---- --00 ---- --00 ---- --00 ---- --uu simc0 111- 0000 111- 0000 111- 0000 uuu- uuuu simc1 1000 0001 1000 0001 1000 0001 uuuu uuuu sima/simc ? 0000 0000 0000 0000 0000 0000 uuuu uuuu simd xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu simtoc 0000 0000 0000 0000 0000 0000 uuuu uuuu eea --xx xxxx --xx xxxx --xx xxxx --uu uuuu eed xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu eec ---- 0000 ---- 0000 ---- 0000 ---- uuuu fc0 0111 0000 0111 0000 0111 0000 uuuu uuuu fc1 0000 0000 0000 0000 0000 0000 uuuu uuuu farl 0000 0000 0000 0000 0000 0000 uuuu uuuu farh 0000 0000 0000 0000 0000 0000 uuuu uuuu fd0l 0000 0000 0000 0000 0000 0000 uuuu uuuu fd0h 0000 0000 0000 0000 0000 0000 uuuu uuuu fd1l 0000 0000 0000 0000 0000 0000 uuuu uuuu fd1h 0000 0000 0000 0000 0000 0000 uuuu uuuu fd ? l 0000 0000 0000 0000 0000 0000 uuuu uuuu fd ? h 0000 0000 0000 0000 0000 0000 uuuu uuuu fd3l 0000 0000 0000 0000 0000 0000 uuuu uuuu fd3h 0000 0000 0000 0000 0000 0000 uuuu uuuu sgc 0000 ---- 0000 ---- 0000 ---- uuuu ---- sgn --00 0000 --00 0000 --00 0000 --uu uuuu sgdnr ---0 0000 ---0 0000 ---0 0000 ---u uuuu opac 0--- 0000 0--- 0000 0--- 0000 u--- uuuu swc 0000 0000 0000 0000 0000 0000 uuuu uuuu daco --00 0000 --00 0000 --00 0000 --uu uuuu ftrc 0--0 --00 0--0 --00 0--0 --00 u--u --uu note: u stands for unchanged x stands for unknown - stands for unimplemented rev. 1.10 ?? de ? e ?? e ? 1 ?? ? 01 ? rev. 1.10 ?7 de?e??e? 1?? ?01? HT45F75 body fat scale flash mcu HT45F75 body fat scale flash mcu ttt ots holtek m icrocontrollers of fer c onsiderable fe xibility on t heir i/ o port s. w ith t he i nput or out put designation of every pin fully under user program control, pull-high selections for all ports and wake-up selections on certain pins, the user is provided with an i/o structure to meet the needs of a wide range of application possibilities. the de vice prov ides bi directional i nput/output l ines l abeled wi th por t na mes p a~pd. t hese i/ o ports are mapped to the ram data memory with specifc addresses as shown in the special purpose data memory table. a ll of thes e i/o ports can be used for input and output operations. for input operation, these ports are non-latch ing, which means the inputs must be ready at the t2 rising edge of instruction mov a, [m], where m denotes the port address. for output operation, all the data is latched and remains unchanged until the output latch is rewritten. pawu d7 d ? d5 d ? d3 d ? d1 d0 papu d7 d ? d5 d ? d3 d ? d1 d0 pa d7 d ? d5 d ? d3 d ? d1 d0 pac d7 d ? d5 d ? d3 d ? d1 d0 pbpu d7 d ? d5 d ? d3 d ? d1 d0 pb d7 d ? d5 d ? d3 d ? d1 d0 pbc d7 d ? d5 d ? d3 d ? d1 d0 pcpu d7 d ? d5 d ? d3 d ? d1 d0 pc d7 d ? d5 d ? d3 d ? d1 d0 pcc d7 d ? d5 d ? d3 d ? d1 d0 pdpu d ? d1 d0 pd d ? d1 d0 pdc d ? d1 d0 i/o registe? list pull-high resisto?s many product applications require pull-high resistors for their switch inputs usually requiring the use of an external resistor . t o eliminate the need for these external resistors, all i/o pins, when confgured as an input have the capability of being connected to an internal pull-high resistor . these pull-high re sistors a re se lected usi ng re gisters p apu~pdpu, a nd a re i mplemented usi ng we ak pmos transistors. na ? e d7 d ? d5 d ? d3 d ? d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~0 port a bit 7 ~ bit 0 pull-high control 0: disable 1: enable rev. 1.10 ?? de?e??e? 1?? ?01? rev. 1.10 ? 7 de ? e ?? e ? 1 ?? ? 01 ? HT45F75 body fat scale flash mcu HT45F75 body fat scale flash mcu bu este bt 7 5 4 na ? e d7 d ? d5 d ? d3 d ? d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~0 port b bit 7 ~ bit 0 pull-high control 0: disable 1: enable na ? e d7 d ? d5 d ? d3 d ? d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~0 port c bit 7 ~ bit 0 pull-high control 0: disable 1: enable na ? e d ? d1 d0 r/w r/w r/w r/w por 0 0 0 bit 7~3 unimplemented, read as "0" bit 2~0 port d bit 2 ~ bit 0 pull-high control 0: disable 1: enable the hal t instruction forces the microcontroller into the sleep or idle mode which preserves power, a feature that is important for battery and other low-power applications. v arious methods exist to wake-up the microcontroller, one of which is to change the logic condition on one of the port a pins from high to low . this function is especially suitable for applications that can be woken up via extern al switches. each pin on port a can be selected individually to have this wake-up feature using the pawu register. na ? e d7 d ? d5 d ? d3 d ? d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~0 port a bit 7~bit 0 w ake-up control 0: disable 1: enable rev. 1.10 ? 8 de ? e ?? e ? 1 ?? ? 01 ? rev. 1.10 ?9 de?e??e? 1?? ?01? HT45F75 body fat scale flash mcu HT45F75 body fat scale flash mcu ot cotol estes each i/o port has its ow n control register known as p ac~pdc, to control the input/output configuration. w ith this control register , each cmos output or input can be reconfigured dynamically under software control. each pin of the i/o ports is directly mapped to a bit in its associated port control register . for the i/o pin to function as an input, the corresponding bit of the control register must be written as a 1. this will then allow the logic state of the input pin to be directly read by instructions. when the corresponding bit of the control register is written as a 0, the i/o pin will be setup as a cmos output. if the pin is currently setup as an output, instructions can still be used to read the output register . however , it should be noted that the program will in fact only read the status of the output data latch and not the actual logic status of the output pin. na ? e d7 d ? d5 d ? d3 d ? d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 1 1 1 1 1 1 1 1 bit 7~0 port a bit 7 ~ bit 0 input/output control 0: output 1: input na ? e d7 d ? d5 d ? d3 d ? d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 1 1 1 1 1 1 1 1 bit 7~0 port b bit 7 ~ bit 0 input/output control 0: output 1: input na ? e d7 d ? d5 d ? d3 d ? d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 1 1 1 1 1 1 1 1 bit 7~0 port c bit 7 ~ bit 0 input/output control 0: output 1: input na ? e d ? d1 d0 r/w r/w r/w r/w por 1 1 1 bit 7~3 unimplemented, read as "0" bit 2~0 port d bit 2 ~ bit 0 input/output control 0: output 1: input rev. 1.10 ?8 de?e??e? 1?? ?01? rev. 1.10 ? 9 de ? e ?? e ? 1 ?? ? 01 ? HT45F75 body fat scale flash mcu HT45F75 body fat scale flash mcu ot soce cet cotol the device supports dif ferent source current driving capability for each i/o port. w ith the corresponding selection register , sledc0 and sledc1, each i/o port can support four levels of the source current driving capability . users should refer to the d.c. charac teristics section to select the desired source current for different applications. sledc0 pbps3 pbps ? pbps1 pbps0 paps3 paps ? paps1 paps0 sledc1 pdps1 pdps0 pcps3 pcps ? pcps1 pcps0 i/o po?t sou??e cu??ent cont?ol registe?s list sledc0 registe? bit 7 ? 5 ? 3 ? 1 0 na ? e pbps3 pbps ? pbps1 pbps0 paps3 paps ? paps1 paps0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 1 0 1 0 1 0 1 bit 7~6 pbps3~pbps2 : pb7~pb4 source current selection 00: source current=level 0 (min.) 01: source current=level 1 10: source current=level 2 11: source current=level 3 (max.) bit 5~4 pbps1~pbps0 : pb3~pb0 source current selection 00: source current=level 0 (min.) 01: source current=level 1 10: source current=level 2 11: source current=level 3 (max.) bit 3~2 paps3~paps2 : pa7~pa4 source current selection 00: source current=level 0 (min.) 01: source current=level 1 10: source current=level 2 11: source current=level 3 (max.) bit 1~0 paps1~paps0 : pa3~pa0 source current selection 00: source current=level 0 (min.) 01: source current=level 1 10: source current=level 2 11: source current=level 3 (max.) na ? e pdps1 pdps0 pcps3 pcps ? pcps1 pcps0 r/w r/w r/w r/w r/w r/w r/w por 0 1 0 1 0 1 bit 7~6 unimplemented, read as 0 bit 5~4 pdps1~pdps0 : pd2~pd0 source current selection 00: source current=level 0 (min.) 01: source current=level 1 10: source current=level 2 11: source current=level 3 (max.) rev. 1.10 70 de ? e ?? e ? 1 ?? ? 01 ? rev. 1.10 71 de?e??e? 1?? ?01? HT45F75 body fat scale flash mcu HT45F75 body fat scale flash mcu bit 3~2 : pc7~pc4 source current selection 00: source current=level 0 (min.) 01: source current=level 1 10: source current=level 2 11: source current=level 3 (max.) bit 1~0 : pc3~pc0 source current selection 00: source current=level 0 (min.) 01: source current=level 1 10: source current=level 2 11: source current=level 3 (max.) i/o pin structures the accompanying diagrams illustrate the internal structures of some generic i/o pin types. as the exact logical construction of the i/o pin will dif fer from these drawings, they are supplied as a guide only to assist with the functional understanding of the i/o pins. the wide range of pin-shared structures does not permit all types to be shown. ??? ?? ? ? ? generic input/output structure programming considerations within the user program, one of the frst things to consider is port initi alisation. after a reset, all of the i/o data and port control registers will be set high. this means that all i/o pins will default to an i nput st ate, t he l evel of whi ch de pends on t he ot her c onnected c ircuitry a nd whe ther pul l-high selections have been chosen. if the port control registers, p ac~pdc, are then programmed to setup some pins as outputs, these output pins will have an initial high output value unless the associated port dat a regi sters, p a~pd, a re frst progra mmed. se lecting whi ch pi ns a re i nputs a nd whi ch a re outputs can be achieved byte-wide by loading the correct values into the appropriate port control register o r b y p rogramming i ndividual b its i n t he p ort c ontrol r egister u sing t he set [ m].i a nd clr [m ].i i nstructions. not e t hat when usi ng t hese bi t c ontrol i nstructions, a re ad-modify-write operation takes place. the microcontroller must frst read in the data on the entire port, modify it to the required new bit values and then rewrite this data back to the output ports. port a has the additional capability of providing wake-up functions. when the device is in the sleep or idle mode, various methods are available to wake the device up. one of these is a high to low transition of any of the port a pins. single or multiple pins on port a can be setup to have this function. rev. 1.10 70 de?e??e? 1?? ?01? rev. 1.10 71 de ? e ?? e ? 1 ?? ? 01 ? HT45F75 body fat scale flash mcu HT45F75 body fat scale flash mcu te modles tm one of the most fundamental functions in any microcontroller device is the ability to control and measure time. t o implement time related functions each device includes several t imer modules, abbreviated t o t he na me t m. t he t ms a re m ulti-purpose t iming un its a nd se rve t o pr ovide operations such as t imer/counter, input capture, compare match output and single pulse output as we ll a s be ing t he fun ctional uni t for t he ge neration of pw m si gnals. e ach of t he t ms ha s t wo individual interrupts. the addition of input and output pins for each tm ensures that users are provided with timing units with a wide and fexible range of features. the common features of the dif ferent tm types are described here with more detailed information provided in the individual compact and periodic tm sections. the device contains three tms having a reference name of tm0, tm1 and tm2. each individual tm can be categorised as a certain type, namely compact t ype tm or periodic t ype tm. although similar in nature, the different tm types vary in their feature complexity. the common features to all of the compact and periodic tms will be described in this section, the detailed operation regarding each of the tm types will be described in separate sections. the main features and dif ferences between the two types of tms are summarised in the accompanying table. ti ? e ? /counte ? i/p captu ? e co ? pa ? e mat ? h output pwm channels 1 1 single pulse output 1 pwm align ? ent edge edge pwm adjust ? ent pe ? iod & duty duty o ? pe ? iod duty o ? pe ? iod tm fun?tion su??a?y tm0 tm1 tm? 10- ? it ctm 10- ? it ptm 10- ? it ptm tm na?e/type refe?en?e tm ope?ation the t wo di fferent t ypes of t m of fer a di verse ra nge of func tions, from sim ple t iming ope rations to pwm signal generation. the key to understanding how the tm operates is to see it in terms of a fre e runni ng c ounter who se va lue i s t hen c ompared wi th t he va lue of pre -programmed i nternal comparators. when the free running counter has the same value as the pre-programmed comparator , known a s a c ompare m atch si tuation, a t m i nterrupt si gnal wi ll be ge nerated whi ch c an c lear t he counter a nd pe rhaps a lso c hange t he c ondition of t he t m ou tput pi n. t he i nternal t m c ounter i s driven by a user selectable clock source, which can be an internal clock or an external pin. the c lock so urce wh ich d rives t he m ain c ounter i n e ach t m c an o riginate f rom v arious so urces. the selection of the required clock source is implemented using the tnck2~tnck0 bits in the tm control registers. the clock source can be a ratio of the system clock f sys or the internal high clock f h , the f sub clock source or the exte rnal tckn pin. the tckn pin cloc k source is used to allow an external signal to drive the tm as an external clock source or for event counting. rev. 1.10 7 ? de ? e ?? e ? 1 ?? ? 01 ? rev. 1.10 73 de?e??e? 1?? ?01? HT45F75 body fat scale flash mcu HT45F75 body fat scale flash mcu tm tets the compact t ype and periodic t ype tms each have two internal interrupts, one for each of the internal c omparator a or c omparator p , whi ch ge nerate a t m i nterrupt whe n a c ompare m atch condition occurs. when a tm interrupt is generated it can be used to clear the counter and also to change the state of the tm output pin. each of the tms, irrespective of what type, has one tm input pin, with the label tckn. the tm input pin is essentially a clock source for the tm and is selected using the tnck2~tnck0 bits in the tmnc0/ptmnc0 register . this external tm input pin allows an external clock source to drive the internal tm. this external tm input pin is shared with other functions but will be connected to the internal tm if selected using the tnck2~tnck0 bits. the tm input pin can be chosen to have either a rising or falling active edge. the tms each have two output pins w ith the label tpn_0 and tpn_1. when the tm is in the compare match output mode, these pins can be controlled by the tm to switch to a high or low level or to toggle w hen a compare match s ituation occurs . the external tp n output pin is also the pin where the tm generates the pwm output waveform. as the tm output pins are pin-shared with other function, the tm output function must frst be setup using the ctrl0 register . a single bit in one of the registers determines if its associated pin is to be used as an external tm output pin or if it is to have another function. the number of output pins for each tm type is dif ferent, the details are provided in the accompanying table. all tm output pin names have a _n suffx. pin names that include a _0 or _1 suffx indicate that they are from a tm with multiple output pins. this allows the tm to generate a complimentary output pair, selected using the i/o register data bits. tp0_0 ? tp0_1 tp1_0 ? tp1_1 tp ? _0 ? tp ? _1 ctrl0 tm output pins tm input/output pin cont?ol registe?s selecting to have a tm input/outpu t or whether to retain its other shared functions is implemented using one register with a single bit in each register corresponding to a tm input/output pin. when the tmn is enabled, if the corresponding pin is setup as a tm input/ou tput, and the complimentary output will be as a normal i/o pin. na ? e tp ? cps tp1cps tp0cps r/w r/w r/w r/w por 0 0 0 bit 7~3 unimplemented, read as 0 bit 2 tp2cps : tp2_0, tp2_1 pin selection 0: tp2_0 1: tp2_1 when tm2 is enabled, the output function of tp2_0 is timer , then the tp2_1 is i/o, and vice versa. rev. 1.10 7? de?e??e? 1?? ?01? rev. 1.10 73 de ? e ?? e ? 1 ?? ? 01 ? HT45F75 body fat scale flash mcu HT45F75 body fat scale flash mcu bit 1 : tp1_0, tp1_1 pin selection 0: tp1_0 1: tp1_1 when tm1 is enabled, the output function of tp1_0 is timer , then the tp1_1 is i/o, and vice versa. bit 0 : tp0_0, tp0_1 pin selection 0: tp0_0 1: tp0_1 when tm0 is enabled, the output function of tp0_0 is timer , then the tp0_1 is i/o, and vice versa. programming considerations the tm counter registers and the capture/compare ccra and ccrp registers, being 10-bit, all have a low and high byte structure. the high bytes can be directly accessed, but as the low bytes can only be accessed via an internal 8-bit buf fer, reading or writing to these register pairs must be carried out in a specifc way . the important point to note is that data transfer to and from the 8-bit buffer and its rela ted low byte only takes place when a write or read operation to its corresponding high byte is executed. as the ccra and ccrp registers are implemented in the way shown in the following diagram and accessing the register is carried out in a specific way described above, it is recommended to use the mov instruction to access the ccra and ccrp low byte registers, named t mxal/ptmxal a nd pt mxrpl, usi ng t he fol lowing a ccess pro cedures. ac cessing the cc ra or cc rp l ow by te re gister wi thout fol lowing t hese a ccess pro cedures wi ll re sult i n unpredictable values. data bus 8-?it buffe? tmxdh/ ptmxdh tmxdl/ ptmxdl ptmxrph ptmxrpl tmxah/ ptmxah tmxal/ ptmxal tm counte? registe? (read only) tm ccra registe? (read/w?ite) tm ccrp registe? (read/w?ite) the following steps show the read and write procedures: ? writing data to ccra or ccrp ? step 1. w rite data to low byte tmxal/ptmxal or ptmxrpl note that here data is only written to the 8-bit buffer. ? step 2. w rite data to high byte tmxah/ptmxah or ptmxrph here data is written directly to the high byte registers and simultaneously data is latched from the 8-bit buffer to the low byte registers. ? reading data from the counter registers and ccra or ccrp ? step 1. read data from the high byte tmxdh/ptmxdh, tmxah/ptmxah or ptmxrph here data is read directly from the high byte registers and simultaneously data is latched from the low byte register into the 8-bit buffer. ? step 2. read data from the low byte tmxdl/ptmxdl, tmxal/ptmxal or ptmxrpl this step reads data from the 8-bit buffer. rev. 1.10 7 ? de ? e ?? e ? 1 ?? ? 01 ? rev. 1.10 75 de?e??e? 1?? ?01? HT45F75 body fat scale flash mcu HT45F75 body fat scale flash mcu coact tye tm ctm although the simplest form of the two t m types, the compact t m type still contains three operating modes, wh ich a re c ompare ma tch ou tput, t imer/event c ounter a nd pw m ou tput m odes. t he compact tm can be controlled with an external input pin and can drive tw o external output pins. these two external output pins can be the same signal or the inverse signal. 10- ? it ctm 0 tck0 tp0_0 ? tp0_1 co?pa?t tm ope?ation at its core is a 10-bit count-up counter which is driven by a user selectable internal or external clock source. t here a re a lso t wo i nternal c omparators wi th t he na mes, com parator a a nd com parator p. t hese c omparators wi ll c ompare t he v alue i n t he c ounter wi th c crp a nd c cra r egisters. t he ccrp is three bits wide whose value is compared with the highest three bits in the counter while the ccra is the ten bits and therefore compares with all counter bits. the onl y way of changi ng the value of the 10-bit count er using the appl ication program , is to clear the counter by changing the tnon bit from low to high. the counter will also be cleared automatically by a counter overfow or a compare match with one of its associated comparators. when these conditions occur , a tm interrupt signal will also usually be generated. the compact type tm can operate in a number of dif ferent operational modes, can be driven by dif ferent clock sources including an input pin and can also control an output pin. all operating setup conditions are selected using relevant internal registers. ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? - - ? ??? ?? ? ??? ? ? ? ? ? ? ?? ? ? ? ? ? ?? ? ?? compact type tm block digram (n=0) rev. 1.10 7? de?e??e? 1?? ?01? rev. 1.10 75 de ? e ?? e ? 1 ?? ? 01 ? HT45F75 body fat scale flash mcu HT45F75 body fat scale flash mcu coact tye tm este escto overall operat ion of t he compa ct tm i s c ontrolled usi ng si x regi sters. a rea d only regi ster pai r exists to store the internal counter 10-bit value, while a read/write register pair exists to store the internal 10-bit ccra value. the remaining two registers are control registers which setup the different operating and control modes as well as the three ccrp bits. tmnc0 tnpau tnck ? tnck1 tnck0 tnon tnrp ? tnrp1 tnrp0 tmnc1 tnm1 tnm0 tnio1 tnio0 tnoc tnpol tndpx tncclr tmndl d7 d ? d5 d ? d3 d ? d1 d0 tmndh d9 d8 tmnal d7 d ? d5 d ? d3 d ? d1 d0 tmnah d9 d8 compact tm register list (n=0) tmnc0 register (n=0) na ? e tnpau tnck ? tnck1 tnck0 tnon tnrp ? tnrp1 tnrp0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7 tnpau : tmn counter pause control 0: run 1: pause the c ounter c an be pa used by se tting t his bi t hi gh. cl earing t he bi t t o z ero re stores normal counter operation. when in a pause condition the tm will remain powered up and continue to consume power. the counter will retain its residual value when this bit changes from low to high and resume counting from this value when the bit changes to a low value again. bit 6~4 tnck2~tnck0 : select tmn counter clock 000: f /4 001: f 010: f /16 011: f /64 100: f 101: reserved 110: tckn rising edge clock 111: tckn falling edge clock these three bits are used to select the clock source for the tm. selecting the reserved clock input will ef fectively disable the internal counter . the external pin clock source can be chosen to be act ive on the rising or falling edge . the clock source f is the system c lock, wh ile f a nd f a re o ther i nternal c locks, t he d etails o f wh ich c an b e found in the oscillator section. bit 3 tnon : tmn counter on/off control 0: off 1: on this bit controls the overall on/of f function of the tm. setting the bit high enables the counter to run, cle aring the bit disables the tm. clearing this bit to zero will stop the counter from counting and turn of f the tm which will reduce its power consumption. when the bit changes state from low to high the internal counter value w ill be res et to zero, however when the bit changes from high to low , the internal counter will retain its residual value. if the tm is in the compare match output mode then the tm rev. 1.10 7 ? de ? e ?? e ? 1 ?? ? 01 ? rev. 1.10 77 de?e??e? 1?? ?01? HT45F75 body fat scale flash mcu HT45F75 body fat scale flash mcu output pin will be reset to its initial condition, as specifed by the tnoc bit, when the tnon bit changes from low to high. bit 2~0 : tmn ccrp 3-bit register, compared with the tmn counter bit 9~bit 7 comparator p match period 000: 1024 tmn clocks 001: 128 tmn clocks 010: 256 tmn clocks 011: 384 tmn clocks 100: 512 tmn clocks 101: 640 tmn clocks 110: 768 tmn clocks 111: 896 tmn clocks these three bits are used to setup the value on the internal ccrp 3-bit register , which are then compared with the internal counter s highest three bits. the result of this comparison c an be se lected t o c lear t he i nternal c ounter i f t he t ncclr bi t i s se t t o zero. set ting t he t ncclr bi t t o z ero e nsures t hat a c ompare m atch wi th t he ccrp values will reset the internal counter . as the ccrp bits are only compared with the highest three counter bits, the compare values exist in 128 clock cycle multiples. clearing a ll t hree bi ts t o z ero i s i n e ffect a llowing t he c ounter t o ove rflow a t i ts maximum value. tmnc1 register (n=0) bit 7 6 5 4 3 2 1 0 na ? e tnm1 tnm0 tnio1 tnio0 tnoc tnpol tndpx tncclr r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~6 : select tmn operating mode 00: compare match output mode 01: undefned 10: pwm mode 11: t imer/counter mode these bits setup the required operating mode for the tm. t o ensure reliable operation the tm should be switched of f before any changes are made to the tnm1 and tnm0 bits. in the t imer/counter mode, the tm output pin control must be disabled. bit 5~4 : select tpn_0, tpn_1 output function compare match output mode 00: no change 01: output low 10: output high 11: t oggle output pwm mode 00: pwm output inactive state 01: pwm output active state 10: pwm output 11: undefned timer/counter mode unused these tw o bits are us ed to determine how the tm output pin changes s tate w hen a certain condition is reached. the function that these bits select depends upon in which mode the tm is running. in t he com pare ma tch out put mode , t he t nio1 a nd t nio0 bi ts de termine how t he tm out put pin changes sta te when a compare ma tch occurs from the com parator a. the tm output pi n can be setup to switch high, switch low or to toggle its present state when a compare match occurs from the comparator a. when the bits are both rev. 1.10 7? de?e??e? 1?? ?01? rev. 1.10 77 de ? e ?? e ? 1 ?? ? 01 ? HT45F75 body fat scale flash mcu HT45F75 body fat scale flash mcu zero, then no change will take place on the output. the initial value of the tm output pin should be setup using the tnoc bit in the tmnc1 register . note that the output level requested by the tnio1 and tnio0 bits must be dif ferent from the initial value setup using the tnoc bit otherwise no change will occur on the tm output pin when a compare match occurs. after the tm output pin changes state, it can be reset to its initial level by changing the level of the tnon bit from low to high. in the pwm mode, the tnio1 and tnio0 bits determine how the tm output pin changes state when a certain compare match condition occurs. the pwm output function i s m odified b y c hanging t hese t wo b its. i t i s n ecessary t o o nly c hange t he values of t he t nio1 a nd t nio0 bi ts onl y a fter t he t mn ha s be en swi tched of f. unpredictable pwm outputs will occur if the t nio1 and t nio0 bits are changed when the tm is running. bit 3 : tpn_0, tpn_1 output control bit compare match output mode 0: initial low 1: initial high pwm mode 0: active low 1: active high this is the output control bit for the tm output pin. its operation depends upon whether tm is being used in the compare match output mode or in the pwm mode. it has no ef fect if the tm is in the t imer/counter mode. in the compare match output mode it determines the logic level of the tm output pin before a compare match occurs. in the pwm mode it determines if the pwm signal is active high or active low. bit 2 : tpn_0, tpn_1 output polarity control 0: non-invert 1: invert this bit controls the polarity of the tpn_0 or tpn_1 output pin. when the bit is set high the tm output pin will be inverted and not inverted when the bit is zero. it has no effect if the tm is in the t imer/counter mode. bit 1 : tmn pwm period/duty control 0: ccrp - period; ccra - duty 1: ccrp - duty; ccra - period this bit, determines which of the ccra and ccrp registers are used for period and duty control of the pwm waveform. bit 0 : select tmn counter clear condition 0: tmn comparatror p match 1: tmn comparatror a match this bi t i s use d t o se lect t he m ethod whi ch c lears t he c ounter. re member t hat t he compact tm contains two comparators, comparator a and comparator p , either of which can be selected to clear the internal counter . w ith the tncclr bit set high, the counter will be cleared when a compare match occurs from the comparator a. when the bit is low , the counter will be cleared when a compare match occurs from the comparator p or with a counter overfow . a counter overfow clearing method can only be implemented if the ccrp bits are all cleared to zero. the tncclr bit is not used in the pwm mode. rev. 1.10 78 de ? e ?? e ? 1 ?? ? 01 ? rev. 1.10 79 de?e??e? 1?? ?01? HT45F75 body fat scale flash mcu HT45F75 body fat scale flash mcu tmndl register (n=0) na ? e d7 d ? d5 d ? d3 d ? d1 d0 r/w r r r r r r r r por 0 0 0 0 0 0 0 0 bit 7~0 d7~d0 : tmn counter low byte register bit 7 ~ bit 0 tmn 10-bit counter bit 7 ~ bit 0 tmndh register (n=0) na ? e d9 d8 r/w r r por 0 0 bit 7~2 unimplemented, read as 0 bit 1~0 d9~d8 : tmn counter high byte register bit 1 ~ bit 0 tmn 10-bit counter bit 9 ~ bit 8 tmnal register (n=0) na ? e d7 d ? d5 d ? d3 d ? d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~0 d7~d0 : tmn ccra low byte register bit 7 ~ bit 0 tmn 10-bit ccra bit 7 ~ bit 0 tmnah register (n=0) na ? e d9 d8 r/w r/w r/w por 0 0 bit 7~2 unimplemented, read as 0 bit 1~0 d9~d8 : tmn ccra high byte register bit 1 ~ bit 0 tmn 10-bit ccra bit 9 ~ bit 8 rev. 1.10 78 de?e??e? 1?? ?01? rev. 1.10 79 de ? e ?? e ? 1 ?? ? 01 ? HT45F75 body fat scale flash mcu HT45F75 body fat scale flash mcu coact tye tm eat modes the compact t ype tm can operate in one of three operating modes, compare match output mode, pwm mo de o r t imer/counter mo de. t he o perating m ode i s se lected u sing t he t nm1 a nd t nm0 bits in the tmnc1 register. to select this mode, bits tnm1 and tnm0 in the tmnc1 register , should be set to 00 respectively . in this mode once the counter is enabled and running it can be cleared by three methods. these are a counter overfow , a compare matc h from comparator a and a compare match from comparator p . when the tncclr bit is low , there are two ways in which the counter can be cleared. one is when a c ompare m atch o ccurs f rom c omparator p , t he o ther i s wh en t he c crp b its a re a ll z ero wh ich allows the counter to overfow . here both tnaf and tnpf interrupt request fags for the comparator a and comparator p respectively, will both be generated. if the tncclr bit in the tmnc1 register is high then the counter will be cleared when a compare match occurs from comparator a. however , here only the tnaf interrupt request flag will be generated even if the value of the ccrp bits is less than that of the ccra registers. therefore when tncclr is high no tnpf interrupt request fag will be generated. if the ccra bits are all zero, the counter will overfow when it reaches its maximum 10-bit, 3ff hex, value, however here the tnaf interrupt request fag will not be generated. as the name of the mode suggests, after a comparison is made, the tm output pin will change state. the tm output pin condition however only changes state when a tnaf interrupt request fag is ge nerated a fter a c ompare m atch oc curs from co mparator a. t he t npf i nterrupt re quest fl ag, generated from a compare match occurs from comparator p , will have no ef fect on the tm output pin. t he wa y i n wh ich t he t m o utput p in c hanges st ate a re d etermined b y t he c ondition o f t he tnio1 and tnio0 bits in the tmnc1 register . the tm output pin can be selected using the tnio1 and tnio0 bits to go high, to go low or to toggle from its present condition when a compare match occurs from com parator a. t he i nitial c ondition of t he t m out put pi n, whi ch i s se tup a fter t he tnon bit changes from low to high, is setup using the tnoc bit. note that if the tnio1 and tnio0 bits are zero then no pin change will take place. rev. 1.10 80 de ? e ?? e ? 1 ?? ? 01 ? rev. 1.10 81 de?e??e? 1?? ?01? HT45F75 body fat scale flash mcu HT45F75 body fat scale flash mcu counte? value 0x3 ff ccrp ccra tnon tnpau tnpol ccrp int . flag tnpf ccra int . flag tnaf tm o / p pin ti?e ccrp =0 ccrp > 0 counte? ove?flow ccrp > 0 counte? ?lea?ed ?y ccrp value pause resu?e stop counte? resta?t tncclr = 0 ; tnm [1:0 ] = 00 output pin set to initial level low if tnoc =0 output toggle with tnaf flag note tnio [1:0 ] = 10 a?tive high output sele?t he?e tnio [1:0 ] = 11 toggle output sele?t output not affe?ted ?y tnaf flag . re?ains high until ?eset ?y tnon ?it output pin reset to initial value output ?ont?olled ?y othe? pin - sha?ed fun?tion output inve?ts when tnpol is high compare match output mode C tncclr=0 (n=0) note: 1. w ith tncclr=0, a comparator p match will clear the counter 2. the tm output pin is controlled only by the tnaf fag 3. the output pin is reset to its initial state by a tnon bit rising edge rev. 1.10 80 de?e??e? 1?? ?01? rev. 1.10 81 de ? e ?? e ? 1 ?? ? 01 ? HT45F75 body fat scale flash mcu HT45F75 body fat scale flash mcu counte? value 0x3 ff ccrp ccra tnon tnpau tnpol ccrp int . flag tnpf ccra int . flag tnaf tm o / p pin ti?e ccra =0 ccra = 0 counte? ove?flow ccra > 0 counte? ?lea?ed ?y ccra value pause resu?e stop counte? resta?t tncclr = 1 ; tnm [1:0 ] = 00 output pin set to initial level low if tnoc =0 output toggle with tnaf flag note tnio [1:0 ] = 10 a?tive high output sele?t he?e tnio [1:0 ] = 11 toggle output sele?t output not affe?ted ?y tnaf flag . re?ains high until ?eset ?y tnon ?it output pin reset to initial value output ?ont?olled ?y othe? pin - sha?ed fun?tion output inve?ts when tnpol is high tnpf not gene?ated no tnaf flag gene?ated on ccra ove?flow output does not ?hange compare match output mode C tncclr=1 (n=0) note: 1. w ith tncclr=1, a comparator a match will clear the counter 2. the tm output pin is controlled only by the tnaf fag 3. the output pin is reset to its initial state by a tnon bit rising edge 4. the tnpf fag is not generated when tncclr=1 rev. 1.10 8 ? de ? e ?? e ? 1 ?? ? 01 ? rev. 1.10 83 de?e??e? 1?? ?01? HT45F75 body fat scale flash mcu HT45F75 body fat scale flash mcu tecote mode to select this mode, bits tnm1 and tnm0 in the tmnc1 register should be set to 1 1 respectively . the t imer/counter m ode operates in an identical w ay to the compare m atch o utput m ode generating the same interrupt fags. the exception is that in the t imer/counter mode the tm output pin is not used. therefore the above description and t iming diagrams for the compare match output mode can be used to understand its function. as the tm output pin is not used in this mode, the pin can be used as a normal i/o pin or other pin-shared function. to select this mode, bits tnm1 and tnm0 in the tmnc1 register should be set to 10 respectively . the pwm functio n within the tm is useful for applications which require functions such as motor control, h eating c ontrol, i llumination c ontrol e tc. b y p roviding a si gnal o f f ixed f requency b ut of varying duty cycle on the tm output pin, a square wave ac waveform can be generated with varying equivalent dc rms values. as both the period and duty cycle of the pwm waveform can be controlled, the choice of generated waveform i s e xtremely fl exible. in t he pwm m ode, t he t ncclr bi t ha s no e ffect on t he pwm operation. bot h of t he ccra a nd ccrp re gisters a re use d t o ge nerate t he pw m wave form, one register is used to clear the internal counter and thus control the pwm waveform frequency , while the other one is used to control the duty cycle. which register is used to control either frequency or duty cycle is determined using the tndpx bit in the tmnc1 register . the pwm waveform frequency and duty cycle can therefore be controlled by the values in the ccra and ccrp registers. an interrupt fag, one for each of the ccra and ccrp , will be generated when a compare match occurs from either comparator a or comparator p . the tnoc bit in the tmnc1 register is used to select the required polarity of the pwm waveform while the two tnio1 and tnio0 bits are used to enable the pwm output or to force the tm output pin to a fxed high or low level. the tnpol bit is used to reverse the polarity of the pwm output waveform. ? ctm, pwm mode, edge-aligned mode, tndpx=0 pe ? iod 1 ? 8 ? 5 ? 38 ? 51 ? ?? 0 7 ? 8 89 ? 10 ?? duty ccra if f sys =16mhz, tm clock source is f sys /4, ccrp=100b and ccra=128, the ctm pwm output frequency=(f sys /4)/512=f sys /2048=7.8125 khz, duty=128/512=25%. if the duty value defned by the ccra register is equal to or greater than the period value, then the pwm output duty is 100%. ? ctm, pwm mode, edge-aligned mode, tndpx=1 pe ? iod ccra duty 1 ? 8 ? 5 ? 38 ? 51 ? ?? 0 7 ? 8 89 ? 10 ?? the pw m o utput p eriod i s d etermined b y t he c cra r egister v alue t ogether wi th t he t m c lock while the pwm duty cycle is defned by the ccrp register value. rev. 1.10 8? de?e??e? 1?? ?01? rev. 1.10 83 de ? e ?? e ? 1 ?? ? 01 ? HT45F75 body fat scale flash mcu HT45F75 body fat scale flash mcu counte? value ccrp ccra tnon tnpau tnpol ccrp int . flag tnpf ccra int . flag tnaf tm o / p pin ( tnoc =1) ti?e counte? ?lea?ed ?y ccrp pause resu?e counte? stop if tnon ?it low counte? reset when tnon ?etu?ns high tndpx = 0 ; tnm [1:0 ] = 10 pwm duty cy?le set ?y ccra pwm ?esu?es ope?ation output ?ont?olled ?y othe? pin - sha?ed fun?tion output inve?ts when tnpol = 1 pwm pe?iod set ?y ccrp tm o / p pin ( tnoc =0) pwm mode C tndpx=0 (n=0) note: 1. here tndpx=0 counter cleared by ccrp 2. a counter clear sets the pwm period 3. the internal pwm function continues even when tnio [1:0]=00 or 01 4. the tncclr bit has no infuence on pwm operation rev. 1.10 8 ? de ? e ?? e ? 1 ?? ? 01 ? rev. 1.10 85 de?e??e? 1?? ?01? HT45F75 body fat scale flash mcu HT45F75 body fat scale flash mcu counte? value ccrp ccra tnon tnpau tnpol ccrp int . flag tnpf ccra int . flag tnaf tm o / p pin ( tnoc =1) ti?e counte? ?lea?ed ?y ccra pause resu?e counte? stop if tnon ?it low counte? reset when tnon ?etu?ns high tndpx = 1 ; tnm [1:0 ] = 10 pwm duty cy?le set ?y ccrp pwm ?esu?es ope?ation output ?ont?olled ?y othe? pin - sha?ed fun?tion output inve?ts when tnpol = 1 pwm pe?iod set ?y ccra tm o / p pin ( tnoc =0) pwm mode C tndpx=1 (n=0) note: 1. here tndpx=1 counter cleared by ccra 2. a counter clear sets the pwm period 3. the internal pwm function continues even when tnio [1:0]=00 or 01 4. the tncclr bit has no infuence on pwm operation rev. 1.10 8? de?e??e? 1?? ?01? rev. 1.10 85 de ? e ?? e ? 1 ?? ? 01 ? HT45F75 body fat scale flash mcu HT45F75 body fat scale flash mcu eodc tye tm tm the pe riodic t ype t m c ontains fv e o perating m odes, wh ich a re c ompare ma tch ou tput, t imer/ event counter , capture input, single pulse output and pwm output modes. the periodic tm can be controlled with an external input pin and can drive two external output pin. 10- ? it ptm 1 ? ? tck1 ? tck ? tp1_0 ? tp1_1 tp ? _0 ? tp ? _1 pe?iodi? tm ope?ation at its core is a 10-bit count-up counter which is driven by a user selectable internal or external clock source. there are two internal comparators with the names, comparato r a and comparator p . these comparators will compare the value in the counter with the ccra and ccrp registers. the onl y way of changing the value of the 10-bit counte r using the appl ication program , is to clear the counter by changing the tnon bit from low to high. the counter will also be cleared automatically by a counter overfow or a compare match with one of its associated comparators. when these conditions occur , a tm interrupt signal will also usually be generated. the periodic type tm can operate in a number of dif ferent operational modes, can be driven by dif ferent clock sources including an input pin and can also control the output pin. all operating setup conditions are selected using relevant internal registers. ? ? ? ? ? ? ? ?? - ? ? ? ? ? ? ? ? ? ? ??? ?? ? ??? ? ? ? ? ? ? ?? ? ? ? ? ? ? ? ? ? ? ? periodic type tm block diagram (n=1 or 2) rev. 1.10 8 ? de ? e ?? e ? 1 ?? ? 01 ? rev. 1.10 87 de?e??e? 1?? ?01? HT45F75 body fat scale flash mcu HT45F75 body fat scale flash mcu eodc tye tm este escto overall operation of the periodic tm is controlled using a series of registers. a read only register pair exists to store the internal counter 10-bit value, while two read/write register pairs exist to store the internal 10-bit ccra and ccrp value. the remaining two registers are control registers which setup the different operating and control modes. ptmnc0 tnpau tnck ? tnck1 tnck0 tnon ptmnc1 tnm1 tnm0 tnio1 tnio0 tnoc tnpol tncapts tncclr ptmndl d7 d ? d5 d ? d3 d ? d1 d0 ptmndh d9 d8 ptmnal d7 d ? d5 d ? d3 d ? d1 d0 ptmnah d9 d8 ptmnrpl d7 d ? d5 d ? d3 d ? d1 d0 ptmnrph d9 d8 10-bit periodic tm register list (n=1 or 2) ptmnc0 register (n=1 or 2) na ? e tnpau tnck ? tnck1 tnck0 tnon r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 bit 7 tnpau : tmn counter pause control 0: run 1: pause the c ounter c an be pa used by se tting t his bi t hi gh. cl earing t he bi t t o z ero re stores normal counter operation. when in a pause condition the tm will remain powered up and continue to consume power. the counter will retain its residual value when this bit changes from low to high and resume counting from this value when the bit changes to a low value again. bit 6~4 tnck2~tnck0 : select tmn counter clock 000: f /4 001: f 010: f /16 011: f /64 100: f 101: reserved 110: tckn rising edge clock 111: tckn falling edge clock these three bits are used to select the clock source for the tm. selecting the reserved clock input will ef fectively disable the internal counter . the external pin clock source can be chosen to be act ive on the rising or falling edge . the clock source f is the system c lock, wh ile f a nd f a re o ther i nternal c locks, t he d etails o f wh ich c an b e found in the oscillator section. rev. 1.10 8? de?e??e? 1?? ?01? rev. 1.10 87 de ? e ?? e ? 1 ?? ? 01 ? HT45F75 body fat scale flash mcu HT45F75 body fat scale flash mcu bit 3 : tmn counter on/off control 0: off 1: on this bit controls the overall on/of f function of the tm. setting the bit high enables the counter to run, cle aring the bit disables the tm. clearing this bit to zero will stop the counter from counting and turn of f the tm which will reduce its power consumption. when the bit changes state from low to high the internal counter value will be reset to zero, however when the bit changes from high to low , the internal counter will retain its residual value until the bit returns high again. if the tm is in the compare match output mode then the tm output pin will be reset to its initial condition, as specifed by the tm output control bit, when the bit changes from low to high. bit 2~0 unimplemented, read as 0 ptmnc1 register (n=1 or 2) bit 7 6 5 4 3 2 1 0 na ? e tnm1 tnm0 tnio1 tnio0 tnoc tnpol tncapts tncclr r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~6 : select tmn operation mode 00: compare match output mode 01: capture input mode 10: pwm mode or single pulse output mode 11: t imer/counter mode these bits setup the required operating mode for the tm. t o ensure reliable operation the tm should be switched of f before any changes are made to the tnm1 and tnm0 bits. in the t imer/counter mode, the tm output pin control must be disabled. bit 5~4 : select tpn_0, tpn_1 output function compare match output mode 00: no change 01: output low 10: output high 11: t oggle output pwm mode/single pulse output mode 00: pwm output inactive state 01: pwm output active state 10: pwm output 11: single pulse output capture input mode 00: input capture at rising edge of tpn_0, tpn_1, tckn 01: input capture at falling edge of tpn_0, tpn_1, tckn 10: input capture at falling/rising edge of tpn_0, tpn_1, tckn 11: input capture disabled timer/counter mode unused these tw o bits are us ed to determine how the tm output pin changes s tate w hen a certain condition is reached. the function that these bits select depends upon in which mode the tm is running. in t he com pare ma tch out put mode , t he t nio1 a nd t nio0 bi ts de termine how t he tm out put pin changes sta te when a compare ma tch occurs from the com parator a. the tm output pin can be setup to switch high, switch low or to toggle its present state when a compare match occurs from the comparator a. when these bits are both zero, then no change will take place on the output. the initial value of the tm output pin should be setup using the tnoc bit. note that the output level requeste d by the tnio1 rev. 1.10 88 de ? e ?? e ? 1 ?? ? 01 ? rev. 1.10 89 de?e??e? 1?? ?01? HT45F75 body fat scale flash mcu HT45F75 body fat scale flash mcu and tnio0 bits must be dif ferent from the initial value setup using the tnoc bit otherwise no change will occur on the tm output pin when a compare match occurs. after the tm output pin changes state, it can be reset to its initial level by changing the level of the tnon bit from low to high. in the pwm mode, the tnio1 and tnio0 bits determine how the tm output pin changes state when a certain compare match condition occurs. the pwm output function i s m odifed by c hanging t hese t wo bi ts. it i s ne cessary t o c hange t he va lues of the tnio1 and tnio0 bits only after the tm has been switched of f. unpredictable pwm outputs will occur if the tnio1 and tnio0 bits are changed when the tm is running. bit 3 : tpn_0, tpn_1 output control bit compare match output mode 0: initial low 1: initial high pwm mode/ single pulse output mode 0: active low 1: active high this is the output control bit for the tm output pin. its operation depends upon whether tm is being used in the compare match output mode or in the pwm mode/ single pulse output mode. it has no ef fect if the tm is in the t imer/counter mode. in the co mpare ma tch out put mode i t de termines t he l ogic l evel of t he t m ou tput pi n before a compare match occurs. in the pwm mode it determines if the pwm signal is active high or active low. bit 2 : tpn_0, tpn_1 output polarity control 0: non-invert 1: invert this bit controls the polarity of the tpn_0, tpn_1 output pin. when the bit is set high the tm output pin will be inverted and not inverted when the bit is zero. it has no effect if the tm is in the t imer/counter mode. bit 1 : tmn capture trigger source select 0: from tpn_0, tpn_1 pin 1: from tckn pin bit 0 : select tmn counter clear condition 0: tmn comparatror p match 1: tmn comparatror a match this bi t i s use d t o se lect t he m ethod whi ch c lears t he c ounter. re member t hat t he periodic t m c ontains t wo c omparators, com parator a a nd com parator p , e ither of which can be selected to clear the internal counter . w ith the tncclr bit set high, the counter will be cleared when a compare match occurs from the comparator a. when the bit is low , the counter will be cleared when a compare match occurs from the comparator p or with a counter overfow . a counter overfow clearing method can only be implemented if the ccrp bits are all cleared to zero. the tncclr bit is not used in the pwm, single pulse or input capture mode. ptmndl register (n=1 or 2) bit 7 6 5 4 3 2 1 0 na ? e d7 d ? d5 d ? d3 d ? d1 d0 r/w r r r r r r r r por 0 0 0 0 0 0 0 0 bit 7~0 : tmn counter low byte register bit 7 ~ bit 0 tmn 10-bit counter bit 7 ~ bit 0 rev. 1.10 88 de?e??e? 1?? ?01? rev. 1.10 89 de ? e ?? e ? 1 ?? ? 01 ? HT45F75 body fat scale flash mcu HT45F75 body fat scale flash mcu ptmndh register (n=1 or 2) na ? e d9 d8 r/w r r por 0 0 bit 7~2 unimplemented, read as 0 bit 1~0 ptmndh : tmn counter high byte register bit 1 ~ bit 0 tmn 10-bit counter bit 9 ~ bit 8 ptmnal register (n=1 or 2) na ? e d7 d ? d5 d ? d3 d ? d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~0 ptmnal : tmn ccra low byte register bit 7 ~ bit 0 tmn 10-bit ccra bit 7 ~ bit 0 ptmnah register (n=1 or 2) na ? e d9 d8 r/w r/w r/w por 0 0 bit 7~2 unimplemented, read as 0 bit 1~0 ptmnah : tmn ccra high byte register bit 1 ~ bit 0 tmn 10-bit ccra bit 9 ~ bit 8 ptmnrpl register (n=1 or 2) na ? e d7 d ? d5 d ? d3 d ? d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~0 ptmnrpl : tmn ccrp low byte register bit 7 ~ bit 0 tmn 10-bit ccrp bit 7 ~ bit 0 ptmnrph register (n=1 or 2) na ? e d9 d8 r/w r/w r/w por 0 0 bit 7~2 unimplemented, read as 0 bit 1~0 ptmnrph : tmn ccrp high byte register bit 1 ~ bit 0 tmn 10-bit ccrp bit 9 ~ bit 8 rev. 1.10 90 de ? e ?? e ? 1 ?? ? 01 ? rev. 1.10 91 de?e??e? 1?? ?01? HT45F75 body fat scale flash mcu HT45F75 body fat scale flash mcu eodc tye tm eat modes the periodic t ype tm can operate in one of fve operating modes, compare match output mode, pwm output mode, single pulse output mode, capture input mode or t imer/counter mode. the operating mode is selected using the tnm1 and tnm0 bits in the ptmnc1 register. to select this mode, bits tnm1 and tnm0 in the ptmnc1 register , should be all cleared to 00 respectively. in this mode once the counter is enabled and running it can be cleared by three methods. these are a counter overfow , a compare match from comparator a and a compare match from comparator p . when the tncclr bit is low , there are two ways in which the counter can be cleared. one is when a compare match occurs from comparator p , the other is when the ccrp bits are all zero which allows the counter to overfow . here both the tnaf and tnpf interrupt request fags for comparator a and comparator p respectively, will both be generated. if the tncclr bit in the ptmnc1 register is high then the counter will be cleared when a compare match occurs from comparator a. however , here only the tnaf interrupt request flag will be generated even if the value of the ccrp bits is less than that of the ccra registers. therefore when tncclr i s h igh n o t npf i nterrupt r equest fa g wi ll b e g enerated. i n t he c ompare ma tch ou tput mode, the ccra cannot be cleared to zero. as the name of the mode suggests, after a comparison is made, the tm output pin, will change state. the tm output pin condition however only changes state when a tnaf interrupt request fag is ge nerated a fter a c ompare m atch oc curs from co mparator a. t he t npf i nterrupt re quest fl ag, generated from a compare match from comparator p , will have no ef fect on the tm output pin. the way in which the tm output pin changes state are determined by the condition of the tnio1 and tnio0 bits in the ptmnc1 register . the tm output pin can be selected using the tnio1 and tnio0 bits to go high, to go low or to toggle from its present condition when a compare match occurs from comparator a. the initial condition of the tm output pin, which is setup after the tnon bit changes from low to high, is setup using the tnoc bit. note that if the tnio1, tnio0 bits are zero then no pin change will take place. rev. 1.10 90 de?e??e? 1?? ?01? rev. 1.10 91 de ? e ?? e ? 1 ?? ? 01 ? HT45F75 body fat scale flash mcu HT45F75 body fat scale flash mcu counte? value 0x3ff ccrp ccra tnon tnpau tnpol ccrp int. flag tnpf ccra int. flag tnaf tm o/p pin ti?e ccrp=0 ccrp > 0 counte? ove?flow ccrp > 0 counte? ?lea?ed ?y ccrp value pause resu?e stop counte? resta?t tncclr = 0; tnm [1:0] = 00 output pin set to initial level low if tnoc=0 output toggle with tnaf flag note tnio [1:0] = 10 a?tive high output sele?t he?e tnio [1:0] = 11 toggle output sele?t output not affe?ted ?y tnaf flag. re?ains high until ?eset ?y tnon ?it output pin reset to initial value output ?ont?olled ?y othe? pin-sha?ed fun?tion output inve?ts when tnpol is high compare match output mode C tncclr=0 (n=1 or 2) note: 1. w ith tncclr=0 a comparator p match will clear the counter 2. the tm output pin is controlled only by the tnaf fag 3. the output pin is reset to initial state by a tnon bit rising edge rev. 1.10 9 ? de ? e ?? e ? 1 ?? ? 01 ? rev. 1.10 93 de?e??e? 1?? ?01? HT45F75 body fat scale flash mcu HT45F75 body fat scale flash mcu counte? value 0x3ff ccrp ccra tnon tnpau tnpol ccrp int. flag tnpf ccra int. flag tnaf tm o/p pin ti?e ccra=0 ccra = 0 counte? ove?flow ccra > 0 counte? ?lea?ed ?y ccra value pause resu?e stop counte? resta?t tncclr = 1; tnm [1:0] = 00 output pin set to initial level low if tnoc=0 output toggle with tnaf flag note tnio [1:0] = 10 a?tive high output sele?t he?e tnio [1:0] = 11 toggle output sele?t output not affe?ted ?y tnaf flag. re?ains high until ?eset ?y tnon ?it output pin reset to initial value output ?ont?olled ?y othe? pin-sha?ed fun?tion output inve?ts when tnpol is high tnpf not gene?ated no tnaf flag gene?ated on ccra ove?flow output does not ?hange compare match output mode C tncclr=1 (n=1 or 2) note: 1. w ith tncclr=1 a comparator a match will clear the counter 2. the tm output pin is controlled only by the tnaf fag 3. the output pin is reset to initial state by a tnon rising edge 4. the tnpf fag is not generated when tncclr=1 rev. 1.10 9? de?e??e? 1?? ?01? rev. 1.10 93 de ? e ?? e ? 1 ?? ? 01 ? HT45F75 body fat scale flash mcu HT45F75 body fat scale flash mcu tecote mode to se lect t his m ode, bi ts t nm1 a nd t nm0 i n t he pt mnc1 re gister sho uld a ll be se t t o 1 1 respectively. the t imer/counter mode operates in an identical way to the compare match output mode generating the same interrupt flags. the exception is that in the t imer/counter mode the tm output pin is not used. therefore the above description and t iming diagrams for the compare match output mode can be used to understand its function. as the tm output pin is not used in this mode, the pin can be used as a normal i/o pin or other pin-shared function. to select this mode, bits tnm1 and tnm0 in the ptmnc1 register should be set to 10 respectively and also the tnio1 and tnio0 bits should be set to 10 respectively . the pwm function within the tm is useful for applications which require functions such as motor control, heating control, illumination control etc. by providing a signal of fxed frequency but of varying duty cycle on the tm output pin, a square wave ac waveform can be generated with varying equivalent dc rms values. as both the period and duty cycle of the pwm waveform can be controlled, the choice of generated waveform i s e xtremely fl exible. in t he pw m m ode, t he t ncclr bi t ha s no e ffect a s t he pw m period. both of the ccrp and ccra registers are used to generate the pwm waveform, one register is used to clear the internal counter and thus control the pwm waveform frequency , while the other one is used to control the duty cycl e. the pwm waveform frequency and duty cycle can therefore be controlled by the values in the ccra and ccrp registers. an interrupt fag, one for each of the ccra and ccrp , will be generated when a compare match occurs from either comparator a or comparator p . the tnoc bit in the ptmnc1 register is used to select the required polarity of the pwm waveform while the two tnio1 and tnio0 bits are used to enable the pwm output or to force the tm output pin to a fxed high or low level. the tnpol bit is used to reverse the polarity of the pwm output waveform. ? pe ? iod 10 ?? 1~10 ? 3 duty ccra if f sys =16mhz, tm clock source select f sys /4, ccrp=100b and ccra=128, the ptm pwm output frequency=(f sys /4) / 512=f sys /2048 =7.8125khz, duty=128/512=25%, if the duty value defned by the ccra register is equal to or greater than the period value, then the pwm output duty is 100%. rev. 1.10 9 ? de ? e ?? e ? 1 ?? ? 01 ? rev. 1.10 95 de?e??e? 1?? ?01? HT45F75 body fat scale flash mcu HT45F75 body fat scale flash mcu counte? value ccrp ccra tnon tnpau tnpol ccrp int. flag tnpf ccra int. flag tnaf tm o/p pin (tnoc=1) ti?e counte? ?lea?ed ?y ccrp pause resu?e counte? stop if tnon ?it low counte? reset when tnon ?etu?ns high tnm [1:0] = 10 pwm duty cy?le set ?y ccra pwm ?esu?es ope?ation output ?ont?olled ?y othe? pin-sha?ed fun?tion output inve?ts when tnpol = 1 pwm pe?iod set ?y ccrp tm o/p pin (tnoc=0) pwm mode (n=1 or 2) note: 1. here counter cleared by ccrp 2. a counter clear sets the pwm period 3. the internal pwm function continues running even when tnio[1:0]=00 or 01 4. the tncclr bit has no infuence on pwm operation rev. 1.10 9? de?e??e? 1?? ?01? rev. 1.10 95 de ? e ?? e ? 1 ?? ? 01 ? HT45F75 body fat scale flash mcu HT45F75 body fat scale flash mcu sle lse tt mode to se lect t his m ode, t he r equired b it p airs, t nm1 a nd t nm0 sh ould b e se t t o 1 0 r espectively a nd a lso the corresponding tnio1 and tnio0 bits should be set to 1 1 respectively . the single pulse output mode, as the name suggests, will generate a single shot pulse on the tm output pin. the trigger for the pulse output lead ing edge is a low to high transition of the tnon bit, which can be implemented using the application program. however in the single pulse mode, the tnon bit can also be made to automatically change from low to high using the external tckn pin, which will in turn initiate the single pulse output. when the tnon bit transitions to a high level, the counter will start running and the pulse leading edge will be generated. the tnon bit should remain high when the pulse is in its active state. the generated pulse trailing edge will be generated when the tnon bit is cleared to zero, which can be implemented using the application program or when a compare match occurs from comparator a. however a compare match from comparator a will also automatically clear the tnon bit and thus generate the single pulse output trailing edge. in this way the ccra value can be used to control the pulse width. a compare match from comparator a will also generate tm interrupts. the counter can only be reset back to zero when the tnon bit changes from low to high when the counter restarts. in the single pulse mode ccrp is not used. the tncclr bit is also not used. ? ? ? ? ? ? ? ? ? ? ? single pulse generation (n=1 or 2) rev. 1.10 9 ? de ? e ?? e ? 1 ?? ? 01 ? rev. 1.10 97 de?e??e? 1?? ?01? HT45F75 body fat scale flash mcu HT45F75 body fat scale flash mcu counte? value ccrp ccra tnon tnpau tnpol ccrp int. flag tnpf ccra int. flag tnaf tm o/p pin (tnoc=1) ti?e counte? stopped ?y ccra pause resu?e counte? stops ?y softwa?e counte? reset when tnon ?etu?ns high tnm [1:0] = 10 ; tnio [1:0] = 11 pulse width set ?y ccra output inve?ts when tnpol = 1 no ccrp inte??upts gene?ated tm o/p pin (tnoc=0) tckn pin softwa?e t?igge? clea?ed ?y ccra ?at?h tckn pin t?igge? auto. set ?y tckn pin softwa?e t?igge? softwa?e clea? softwa?e t?igge? softwa?e t?igge? single pulse mode (n=1 or 2) note: 1. counter stopped by ccra 2. ccrp is not used 3. the pulse is triggered by the tckn pin or by setting the tnon bit high 4. a tckn pin active edge will automatically set the tnon bit high 5. in the single pulse mode, tnio [1:0] must be set to 11 and cannot be changed. rev. 1.10 9? de?e??e? 1?? ?01? rev. 1.10 97 de ? e ?? e ? 1 ?? ? 01 ? HT45F75 body fat scale flash mcu HT45F75 body fat scale flash mcu cate t mode to select this mode bits tnm1 and tnm0 in the ptmnc1 register should be set to 01 respectively . this mode enables external s ignals to capture and s tore the pres ent value of the internal counter and can therefore be used for applic ations such as pulse width measurements. the external signal is supplied on the tpn_0, tpn_1 or tckn pin, selected by the tncapts bit in the ptmnc1 register . the input pin active edge can be eit her a rising edge, a falling edge or both rising and falling edges; the active edge transition type is selected using the tnio1 and tnio0 bits in the ptmnc1 register . the counter is started when the tnon bit changes from low to high which is initiated using the application program. when the required edge transition appears on the tpn_0, tpn_1 or tckn pin the present value in the counter will be latched into the ccra register and a tm interrupt generated. irrespective of what events occur on the tpn_0, tpn_1 or tckn pin the counter will continue to free run until the tnon bit changes from high to low . when a ccrp compare match occurs the counter will reset back to zero; in this way the ccrp value can be used to control the maximum counter value. when a ccrp compare match occurs from comparator p , a tm interrupt will also be generated. counting the number of overfow interrupt signals from the ccrp can be a useful method in measuring long pulse wi dths. the tnio1 and tnio0 bit s ca n se lect the ac tive tri gger edge on the tpn_0, tpn_1 or tckn pin to be a rising edge, falling edge or both edge types. if the tnio1 and tnio0 bits are both set high, then no capture operation will take place irrespective of what happens on the tpn_0, tpn_1 or tckn pin, however it must be noted that the counter will continue to run. as the tpn_0, tpn_1 or tckn pin is pin shared with other functions, care must be taken if the tmn is in the capture input mode. this is because if the pin is setup as an output, then any transitions on this pin may cause an input capture operation to be executed. the tncclr, tnoc and tnpol bits are not used in this mode. rev. 1.10 98 de ? e ?? e ? 1 ?? ? 01 ? rev. 1.10 99 de?e??e? 1?? ?01? HT45F75 body fat scale flash mcu HT45F75 body fat scale flash mcu counte? value yy ccrp tnon tnpau ccrp int. flag tnpf ccra int. flag tnaf ccra value ti?e counte? ?lea?ed ?y ccrp pause resu?e counte? reset tnm [1:0] = 01 tm ?aptu?e pin tpn_x o? tckn xx counte? stop tnio [1:0] value xx yy xx yy a?tive edge a?tive edge a?tive edge 00 C rising edge 01 C falling edge 10 C both edges 11 C disa?le captu?e capture input mode (n=1 or 2) note: 1. tnm[1:0]=01 and active edge set by the tnio[1:0] bits 2. a tm capture input pin active edge transfers counter value to ccra 3. the tncclr bit is not used 4. no output function tnoc and tnpol bits are not used 5. ccrp determin es the counter value and the counter has a maximum count value when ccrp is equal to zero rev. 1.10 98 de?e??e? 1?? ?01? rev. 1.10 99 de ? e ?? e ? 1 ?? ? 01 ? HT45F75 body fat scale flash mcu HT45F75 body fat scale flash mcu internal power supply this device contains the ldo and vcm for the regulated power supply . the accompanying block diagram illustrates the basic functional operation. the internal ldo can provide the fixed voltage for pga, adc or the external components; as well the vcm can be used as the reference voltage for adc module. there are four ldo voltage levels, 2.4v , 2.6v , 2.9v or 3.3v , decided by ldovs1~ldovs0 bits in the p wrc regis ter, as w ell the v cm has tw o output voltage levels , 1.05v or 1.25v , s elected by the v cms bit in the p gac1 regis ter. the ld o and v cm functions can be controlled by the enldo and envcm bits respectively and can be powered of f to reduce the power consumption. in addition, the ldo bypass function can be enabled or disabled by the ldobps bit in the register. bypass enldo ldo vcm ?.? ?.? ?.? 3.3 1.05 1.?5 ldovs[1:0] fo? pga? adc powe? pga analog ?o??on ?ode voltage 1.05v o? 1.?5v vcms envcm vdd vout/avdd fo? senso? powe? vcm ldobps internal power supply block diagram registers output voltage adoff enldo envcm vout/avdd vcm 1 0 x disa ? le disa ? le 1 1 x ena ? le disa ? le 0 0 0 disa ? le disa ? le 0 1 0 ena ? le disa ? le 0 0 1 disa ? le disa ? le 0 1 1 ena ? le ena ? le x ? eans dont ? a ? e power control table rev. 1.10 100 de ? e ?? e ? 1 ?? ? 01 ? rev. 1.10 101 de?e??e? 1?? ?01? HT45F75 body fat scale flash mcu HT45F75 body fat scale flash mcu pwrc register bit 7 6 5 4 3 2 1 0 na ? e enldo envcm ldobps ldovs1 ldovs0 r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 bit 7 enldo : ldo function control bit 0: disable 1: enable if the ldo is disabled, there will be no power consumption and ldo output pin is foating. bit 6 envcm : vcm function control bit 0: disable 1: enable if the vcm is disabled, there will be no power consumption and vcm output pin is foating. bit 5~3 unimplemented, read as 0 bit 2 ldobps : ldo bypass function control bit 0: disable 1: enable bit 1~0 ldovs1~ldovs0 : ldo output voltage selection 00: 2.4v 01: 2.6v 10: 2.9v 11: 3.3v pgac1 register bit 7 6 5 4 3 2 1 0 na ? e vcms inis dcset ? dcset1 dcset0 r/w r/w r/w r/w r/w r/w por 1 0 0 0 0 bit 7 vcms : analog common mode voltage selection 0: 1.05v 1: 1.25v bit 6 inis : the selected input ends, in1 and in2, connection control bit described elsewhere. bit 5~4 unimplemented, read as 0 bit 3~1 dcset2~dcset0 : the di+/di- differential input offset voltage adjustment control described elsewhere. bit 0 unimplemented, read as 0 rev. 1.10 100 de?e??e? 1?? ?01? rev. 1.10 101 de ? e ?? e ? 1 ?? ? 01 ? HT45F75 body fat scale flash mcu HT45F75 body fat scale flash mcu analog to digital converter C adc the need to interface to real world analog signals is a common requirement for many electronic systems. however , to properly process these signals by a microcontroller , they must first be converted into digital signals by a/d converters. by integrating the a/d conversion electronic circuitry into the microcontroller , the need for external components is reduced signifcantly with the corresponding follow-on benefts of lower costs and reduced component space requirements. a/d overview this device contains a high accuracy multi-channel 20-bit delta-sigma analog-to-digital (?a/d) converter which can directly interface to external analog signals, such as that from sensors or other control signals and convert these signal s di rectly into a 20-bit di gital va lue. in addit ion, the pga gain control, adc gain control and adc reference gain control determine the amplifcation gain for adc input signal. the des igner can select the best gain combination for the des ired amplifcation applied to the input signal. the following block diagram illustrates the adc basic operational function. the adc input channel can be arranged as two dif ferential input channels. the input signal can be amplifed by pga before entering the 20-bit delta-sigma adc. the ?adc modulator will output one bit converted data to sinc flter which can transform the converted one-bit data to 20 bits and store them into the specifc data registers. additionally , this device also provides a temperature sensor to compensate the a/d converter deviation caused by the temperature. w ith high accuracy and performance, this device is very suitable for scale related products. vdd/5 vcm an0 an? vtso+ rfc chsp[?:0] an1 an3 vtso- chsn[?:0] pgs=x1?x??x??x8?x1 ??x3??x???x1?8 in1 in? inis di- di+ refp refn vgs= x1? x1/?? x1/? ags= x1? x?? x?? x8 ?0-?it adc vcm dcset[?:0] sinc filte? ador[?:0] adrst buffe? vrp vrn 01 vcm vrefp 01 avss vrefn vrefs vcm 000 001 101 110 111 000 001 101 110 111 vrbufp vrbufn a/d converter structure rev. 1.10 10 ? de ? e ?? e ? 1 ?? ? 01 ? rev. 1.10 103 de?e??e? 1?? ?01? HT45F75 body fat scale flash mcu HT45F75 body fat scale flash mcu a/d data rate defnition the delta-sigma adc data rate can be calculated using the equation s below: data rate=(adc clock) / (flms[2:0] ador[2:0]) where the adc clock is sourced from f mclk and flms[2:0] select s the adc mode and defne s a constant number which can only be 30 or 12 . also ador[2:0] defne s the chopper average function and the over-sampling rating (osr). for exam ple, if a data rate of 10hz is desired , then for a 4.8mhz adc clock, set flms[2:0]=000b (adc output in normal mode and clock divided by 30) . then set ador[2:0]=001b to define chopper=2 and osr=8192. thus the data rate=4.8mhz / (30 2 8192)=10hz i n addition, the a/d converter can provide a data rate of 3.2khz for auto power on. a/d converter register description overall operation of the a/d converter is controlled using 9 registers. a group of read only registers exist to store the adc data 20-bit value. the remaining six registers are control registers which set up the gain selections and control functions of the a/d converter. register name bit 7 6 5 4 3 2 1 0 pgac0 vgs1 vgs0 ags1 ags0 pgs ? pgs1 pgs0 pgac1 vcms inis dcset ? dcset1 dcset0 pgacs chsn ? chsn1 chsn0 chsp ? chsp1 chsp0 adrl d7 d ? d5 d ? d3 d ? d1 d0 adrm d15 d1 ? d13 d1 ? d11 d10 d9 d8 adrh d19 d18 d17 d1 ? adcr0 adrst adslp adoff ador ? ador1 ador0 vrefs adcr1 flms ? flms1 flms0 vrbufn vrbufp adcdl eoc adcs adck ? adck3 adck ? adck1 adck0 a/d converter register list programmable gain amplifer C pga there are three registers related to the programmable gain control, pgac0, pgac1 and pgacs. the pgac0 resister is used to select the pga gain, adc gain and the adc reference gain. as well, the pgac1 register is used to define the input connection, dif ferential input of fset voltage adjustment control and the vcm voltage selection. in addition, t he pgacs register is used to select the input ends for the pga. therefore, the input channels have to be determined by the chsp2~0 and chsn2~0 bits to determine which analog channel input pins, rfc pin, temperature detector inputs or internal power supply are actually connected to the internal differential a/d converter. rev. 1.10 10? de?e??e? 1?? ?01? rev. 1.10 103 de ? e ?? e ? 1 ?? ? 01 ? HT45F75 body fat scale flash mcu HT45F75 body fat scale flash mcu pgac0 register bit 7 6 5 4 3 2 1 0 na ? e vgs1 vgs0 ags1 ags0 pgs ? pgs1 pgs0 r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 bit 7 unimplemented, read as 0 bit 6~5 vgs1~vgs0 : v ref gain selection 00: 1 01: 1/2 10: 1/4 11: reserved bit 4~3 ags1~ags0 : adc gain selection 00: 1 01: 2 10: 4 11: 8 bit 2~0 pgs2~pgs0 : pga gain selection 000: 1 001: 2 010: 4 011: 8 100: 16 101: 32 110: 64 111: 128 pgac1 register bit 7 6 5 4 3 2 1 0 na ? e vcms inis dcset ? dcset1 dcset0 r/w r/w r/w r/w r/w r/w por 1 0 0 0 0 bit 7 vcms : analog common mode voltage selection 0: 1.05v 1: 1.25v bit 6 inis : the selected input ends, in1 and in2, connection control bit 0: not shorted 1: shorted bit 5~4 unimplemented, read as "0" bit 3~1 dcset2~dcset0 : the di+/di- differential input offset voltage adjustment control 000: +0v 001: +0.25v r 010: +0.5v r 011: +0.75v r 100: +0v 101: -0.25v r 110: -0.5v r 111: -0.75v r bit 0 unimplemented, read as "0" rev. 1.10 10 ? de ? e ?? e ? 1 ?? ? 01 ? rev. 1.10 105 de?e??e? 1?? ?01? HT45F75 body fat scale flash mcu HT45F75 body fat scale flash mcu pgacs register bit 7 6 5 4 3 2 1 0 na ? e chsn ? chsn1 chsn0 chsp ? chsp1 chsp0 r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 bit 7~6 unimplemented, read as 0 bit 5~3 chsn2~chsn0 : pga negative input ends selection 000: an1 001: an3 010: reserved 011: reserved 100: reserved 101: vdd/5 110: vcm 111: t emperature sensor vtso- bit 2~0 chsp2~chsp0 : pga positive input ends selection 000: an0 001: an2 010: reserved 011: reserved 100: reserved 101: rfc C the rfc is a single-end input, if selected, then the pga negative input must select vcm, an1 or an3. 110: vcm 111: t emperature sensor vtso+ note: if the pga is assigned to have a single end input on di+, then the di- input must select vcm. a/d converter data registers C adrl, adrm, adrh this device conta ins an internal 20-bit ?a/d converter , it requires three data registers to store the converted value. these are a high byte register , known as adrh, adrm and a low byte register , known as adrl . aft er the conversion process takes place, these registers can be directly read by the microcontroller to obtain the digitised conversion value. d0~d19 are the a/d conversion result data bits. adrh register bit 7 6 5 4 3 2 1 0 na ? e d19 d18 d17 d1 ? r/w r r r r por x x x x x unknown bit 7~4 unimplemented, read as 0 bit 3~0 a/d conversion data register bit 19~bit 16 adrm register bit 7 6 5 4 3 2 1 0 na ? e d15 d1 ? d13 d1 ? d11 d10 d9 d8 r/w r r r r r r r r por x x x x x x x x x unknown bit 7~0 a/d conversion data register bit 15~bit 8 rev. 1.10 10? de?e??e? 1?? ?01? rev. 1.10 105 de ? e ?? e ? 1 ?? ? 01 ? HT45F75 body fat scale flash mcu HT45F75 body fat scale flash mcu adrl register bit 7 6 5 4 3 2 1 0 na ? e d7 d ? d5 d ? d3 d ? d1 d0 r/w r r r r r r r r por x x x x x x x x x unknown bit 7~0 a/d conversion data register bit 7~bit 0 a/d converter control registers C adcr0, adcr1, adcs to control the function and operation of the a/d converter, three control registers known as adcr0, adcr1 and a dcs are provided. these 8-bit registers define functions s uch as the s election of which reference source is used to the internal adc, the adc clock source, the adc output data rate as well as controlling the power-up function and monitoring the adc end of conversion status. adcr0 register bit 7 6 5 4 3 2 1 0 na ? e adrst adslp adoff ador ? ador1 ador0 vrefs r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 1 0 0 0 0 bit 7 adrst : adc software reset control bit. 0: disable 1: enable this bit is used to reset the adc internal digital sinc flter . the bit is normally low but if set high and then cleared low again, the a/d converter will initiate a conversion process data. bit 6 adslp : adc sleep mode control bit 0: normal mode 1: sleep mode this bit i s u sed fo r adc sl eep m ode control b it. t o se t t his bit h igh wi ll fo rce t he adc enter sleep mode which can reduce the power consumption and prevent the adc start- up time. bit 5 adoff : adc module power on/off control bit 0: adc module power on 1: adc module power off this bit controls the power of the adc module. this bit should be cleared to zero to enable the a/d converter . if the bit is set high then the adc will be switched off re ducing t he de vice powe r c onsumption. as t he adc wi ll c onsume a l imited amount of power , even when not executing a conversion, this may be an important consideration in power sensitive battery powered applications. note: 1. it is recommended to set adoff=1 before entering idle/sleep mode for saving power. 2. adoff=1 will power down the adc module, no matter the settings of adslp and adrst bits. 3. t he r elationship a bout t hese b its, adoff , adsl p a nd adr st wi ll b e further described elsewhere. bit 4 ~ 2 ador2~ador0 : output data rate selection normal mode: output data rate 000: chop=2, osr=16384 001: chop=2, osr=8192 010: chop=2, osr=4096 011: chop=2, osr=2048 rev. 1.10 10 ? de ? e ?? e ? 1 ?? ? 01 ? rev. 1.10 107 de?e??e? 1?? ?01? HT45F75 body fat scale flash mcu HT45F75 body fat scale flash mcu 100: chop=2, osr=1024 101: chop=2, osr=512 110: chop=2, osr=256 111: chop=2, osr=128 low latency mode: output data rate 000: chop=1, osr=16384 001: chop=1, osr=8192 010: chop=1, osr=4096 011: chop=1, osr=2048 100: chop=1, osr=1024 101: chop=1, osr=512 110: chop=1, osr=256 111: chop=1, osr=128 bit 1 unimplemented, read as "0" bit 0 vrefs : adc reference source selection 0: internal reference (vcm, a vss) 1: external reference (vrefp, vrefn) adcr1 register bit 7 6 5 4 3 2 1 0 na ? e flms ? flms1 flms0 vrbufn vrbufp adcdl eoc r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 bit 7 ~ 5 flms2~flms0 : adc output data mode and clock division ratio selection 000: normal mode, adc clock /30 010: normal mode, adc clock /12 100: low latency mode, adc clock /30 110: low latency mode, adc clock /12 others: reserved bit 4 vrbufn : vrn buffer enable 0: disable 1: enable bit 3 vrbufp : vrp buffer enable 0: disable 1: enable bit 2 adcdl : adc converted data latch function 0: disable data latch 1: enable data latch if the a dc converted data latch function is enabled, the lates t converted data value will be latched and not be updated by any subsequent converted res ults until this function is disable d. although the converted data is latched into the data registers, the adc circuits remain operational, but will not generate interrupt and eoc will not change. it is recommended that this bit should be set high before reading the converted data in the adrl, adrm and adrh registers. after the converted data has been read out, the bit can then be cleared to low to disable the adc data lat ch function and allow further conversion values to be stored. in this way , the possibility of obtaining undesired data during adc conversions can be prevented. bit 1 eoc : end of a/d conversion fag 0: a/d conversion in progress 1: a/d conversion ended this bit must be cleared by software. bit 0 unimplemented, read as 0 rev. 1.10 10? de?e??e? 1?? ?01? rev. 1.10 107 de ? e ?? e ? 1 ?? ? 01 ? HT45F75 body fat scale flash mcu HT45F75 body fat scale flash mcu adcs register bit 7 6 5 4 3 2 1 0 na ? e adck ? adck3 adck ? adck1 adck0 r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 bit 7~5 unimplemented, read as 0 bit 4~0 adck4~adck0 : select adc clock source (f mclk ) 00000~11110: f /2 / (adck[4:0]+1) 11111: f due to the adc clock source , f mclk , is t ypically designed as 4.8mhz and the mcu might be s elected to w ork at dif ferent s ystem clock, therefore, the designer s hould use the adck4~adck0 bits to get the fixed 4.8mhz adc working clock source. for example, if the system clock is 9. 6 mhz, the adck[4:0] must be 0 to get the mclk =4.8mhz. a/d operation the adc provides three operational modes, which are power down mode, sleep mode and reset mode, controlled respectively by the adoff , adslp and adrst bits in the adcr0 register . the following table illustrates the operating mode selection. adoff adslp adrst operating mode description 1 x x powe ? down ? ode pga off ? adc off 0 1 x sleep ? ode pga on ? adc off 0 0 1 reset ? ode pga on ? adc on ? sinc reset x unknown a/d operation mode selection to enable the adc, the frst step is to disable the adc power down and sleep mode, to make sure the adc is powered up. the adrst bit in the adcr0 register is used to start and reset the a/d converter after power on. when the microcontroller sets this bit from low to high and then low again, an analog to digital converted data in sinc flter will be initiated. after this setup is complete, the adc is ready for operation. these three bits are used to control the overall start operation of the internal analog to digital converter. the eoc bit in the adcr1 register is used to indicate when the analog to digital conversion process is complete. this bit will be autom atically set high by the microcontro ller after a conversion cycle has ended. in addition, the corresponding a/d int errupt request flag will be set in the interrupt control register , and if the interrupts are enabled, an appropriate internal interrupt signal will be generated. this a/d internal interrupt signal will direct the program flow to the associated a/d internal interrupt address for processing. if the a/d internal interrupt is disabled, the microcontroller can be used to poll the eoc bit in the adcr1 register to check whether it has been set 1 as an alternative method of detecting the end of an a/d conversion cycle. the adc converted data will be updated continuous ly by the new converted data. if the a dc converted data latch function is enabled, t he l atest c onverted da ta wi ll be l atched a nd t he fol lowing ne w c onverted da ta wi ll be discarded until this data latch function is disabled. the clock source for the a/d converter should be typically fixed at a value of 4.8mhz, which originates from the system clock f , and can be chosen to be either f or a subdivided version of f . the division rati o value is determined by the adck4~adck0 bits in the adcs register to obtain a 4.8mhz clock source for the adc. the dif ferential reference voltage supply to the a/d converter can be supplied from either the internal power supply pins, vcm and a vss, or from an external reference source supplied on pins, vrefp and vrefn. the desired selection is made using the vrefs bit in the adcr0 register. rev. 1.10 108 de ? e ?? e ? 1 ?? ? 01 ? rev. 1.10 109 de?e??e? 1?? ?01? HT45F75 body fat scale flash mcu HT45F75 body fat scale flash mcu summary of a/d conversion steps the following summarises the individual steps that should be executed in order to implement an a/ d conversion process. ? step 1 enable power ldo, vcm for pga and adc. ? step 2 select pga, adc and v ref gain by pgac0 register. ? step 3 select pga setting for input pins connection and v cm option by pgac1 register. ? step 4 select t he r equired a/ d c onversion c lock 4 .8mhz b y c orrectly p rogramming b its adck4~adck0 in the adcs register. ? step 5 select output data rate. ? step 6 select whi ch c hannel i s t o be c onnected t o t he i nternal pga by c orrectly program ming t he chsp2~chsp0 and chsn2~chsn0 bits which are also contained in the pgacs register. ? step 7 release power down mode and sleep mode by adoff and adslp bits in adcr0 register. ? step 8 reset the a/d by setting the adrst to high in the adcr0 register and clearing this bit to zero to release reset status. ? step 9 if the interrupts are to be used, the interrupt control registers must be correctly configured to ensure the a/d converter interrupt function is active. the master inter rupt control bit, emi, and the a/d converter interrupt bit, ade, must both be set high to do this. ? step 10 to check when the analog to digital conversion process is complete, the eoc bit in the adcr1 register ca n be poll ed. the conversion proc ess is com plete when thi s bit goes l ow. when thi s occurs the a /d data registers a drl, a drm and a drh can be read to obtain the convers ion value. as an alternative method, if the interrupts are enabled and the stack is not full, the program can wait for an a/d interrupt to occur. note: when check ing for the end of the conversion process, if the meth od of polling the eoc bit in the adcr1 register is used, the interrupt enable step above can be omitted. programming considerations during m icrocontroller ope rations where t he a/d c onverter i s not be ing use d, t he a/d i nternal circuitry can be switched of f to reduce power consumption, by setting bit adoff high in the adcr0 r egister. w hen t his h appens, t he i nternal a/ d c onverter c ircuits wi ll n ot c onsume p ower irrespective of what analog voltage is applied to their input lines. rev. 1.10 108 de?e??e? 1?? ?01? rev. 1.10 109 de ? e ?? e ? 1 ?? ? 01 ? HT45F75 body fat scale flash mcu HT45F75 body fat scale flash mcu a/d transfer function this device contains a 20-bit ?a/d converter , its full-scale converted digitised value is from 524287 to -524288 in decimal value. the converted data format is formed by a two s complement binary value. the m sb of the converted data is the s igned bit. s ince the full-s cale analog input value is equal to the v cm or ?v ref voltage, selected by the vrefs bit in adcr0 register , this gives a single bit analog input value of v cm or ?v ref divided by 524288. 1 lsb= (v cm or ?v ref ) /524288 the a/d converter input voltage value can be calculated using the following equation: si_i=(pgagn adgn di) + (dcset vr_i) vr_i=vregn vr adc_conversion_data=(si_i vr_i) k where k is equal to 2 19 note: the pgagn, adgn, vregn values are decided by pgs, ags, vgs control bits. ?si_i: differential input signal after process pgagn: programmable gain amplifer gain adgn: adc gain ?di : differential input signal dcset: offset voltage ?vr : differential reference voltage ?vr_i: differential reference input voltage after process vregn: reference voltage gain due to the digital system design of the ?adc, the maximum number of the adc converted value is 524287 a nd t he m inimum va lue i s -524288, t herefore, we c an ha ve t he m iddle num ber 0. t he adc_conversion_data equation illustrates this range of converted data variation. a/d conversion data (2s compliment, hexadecimal) decimal value 0x7ffff 5 ??? 87 0x80000 -5 ??? 88 the above adc conversion data table illustrates the range of adc conversion data. the following diagram shows the relationship between the dc input value and the adc converted data which is presented by the t wos complement. rev. 1.10 110 de ? e ?? e ? 1 ?? ? 01 ? rev. 1.10 111 de?e??e? 1?? ?01? HT45F75 body fat scale flash mcu HT45F75 body fat scale flash mcu ?0 digital output two's ?o?ple?ent dc input value 0111 1111 1111 1111 1111 1000 0000 0000 0000 0000 vregn dcset vrefn vrefp ainaip vregn adgn pgagn ? ? ? ? ? 0 a/d converted data the adc converted data is related to the input voltage and the pga selections. the format of the adc output is a two s complement binary code. the length of this output code is 20 bits and the msb is a signed bit. when the msb is 0, which represents the input is positive, on the other hand, as the msb is 1, it represents the input is negative. the maximum value is 524287 and the minimum value is -524288. if the input signal is over the maximum value, the converted data is limited by the 524287, and if the input signal is less than the minimum value, the converted data is limited by -524288. a/d converted data to voltage the designer can recover the converted data by the following equations: if msb=0 (positive converted data): input v oltage=(converted data-0) (lsb/ pga) if the msb=1(negative converted data): input voltage= (twos complement of converted data-0) (lsb/pga) note: t wos complement=ones complement +1 rev. 1.10 110 de?e??e? 1?? ?01? rev. 1.10 111 de ? e ?? e ? 1 ?? ? 01 ? HT45F75 body fat scale flash mcu HT45F75 body fat scale flash mcu a/d programming example example: using an eoc polling method to detect the end of conversion #include HT45F75.inc data .section ' data' adc_result_data_l db ? adc_result_data_m db ? adc_result_data_h db ? code .section code start: c lr a de ; disable adc interrupt mov a, 0 c3h ; po wer c ontrol fo r p ga, a dc mov pwrc, a ; p wrc=11000011, l do e nable, v cm e nable, ; l do b ypass d isable, l do o utput v oltage: 3 .3v m ov a, 000h mov pgac0, a ; p ga ga in=1, a dc ga in=1, v ref ga in=1 m ov a, 080h mov pgac1, a ; v cm =1.25v, i nis, d cset2~0 i n d efault v alue set vrbufp ; e nable b uffer f or v ref+ set vrbufn ; e nable b uffer f or v ref- set vrefs ; f or u sing e xternal re ference clr ador2 ; f or 10 hz o utput d ata r ate, a dor[2:0]=001, f lms[2:0]=000 clr ador1 set ador0 clr flms2 c l r f l m s 1 c l r f l m s 0 clr adoff ; ad c e xit p ower do wn m ode. set adrst ; a dc i n r eset m ode clr adrst ; a dc i n c onversion (c ontinues m ode) clr eoc ; c lear eoc f ag loop: snz eoc ; p olling eoc f ag jmp loop ; w ait f or r ead d ata clr adc_result_data_h clr adc_result_data_m clr adc_result_data_l m o v a , a d r l mov adc_result_data_l, a ; g et l ow b yte a dc v alue m o v a , a d r m mov adc_result_data_m, a ; g et m iddle b yte a dc v alue m o v a , a d r h mov adc_result_data_h, a ; g et h igh b yte a dc v alue get_adc_value_ok: clr eoc ; c learing re ad f ag j mp l oop ; for next data read end rev. 1.10 11 ? de ? e ?? e ? 1 ?? ? 01 ? rev. 1.10 113 de?e??e? 1?? ?01? HT45F75 body fat scale flash mcu HT45F75 body fat scale flash mcu temperature sensor this device provides an internal temperature sensor to compensate the device due to temperature effects. by selecting the pga input channels to be vtso+ and vtso-, the adc can obtain temperature inform ation and the designer can then im plement som e compe nsation on the a/d converted data. the following block diagram illustrates the functional operation of the temperature sensor. avss i avdd adc v tso + v tso - pga serial interface module C sim this device contains a serial interface module, which includes both the four line spi interface and the two line i 2 c interface types, to allow an easy method of communication with external peripheral hardware. having relatively simple communication protocols, these serial interface types allow the microcontroller to interface to external spi or i 2 c based hardware such as sensors, flash memory , etc. as both interf ace types share the same pins and registers, the choice of whether the spi or i 2 c type is used is made using the sim operating mode control bits, named sim2~sim0, in the simc0 register. these pull-high resistors of the sim pin-shared i/o pins are selected using pull-high control registers when the sim function is enabled and the corresponding pins are used as sim input pins. spi interface the spi interface is often used to communicate with external peripheral devices such as sensors, flash memory devices etc. originally developed by motorola, the four line spi interface is a synchronous seri al data interface that has a relatively simple communicat ion prot ocol simplifyi ng the programming requirements when communicating with external hardware devices. the communication is full duplex and operates as a slave/master type, where the device can be either mas ter or s lave. a lthough the s pi interface s pecifcation can control multiple s lave devices from a si ngle m aster, but t his de vice i s provi ded onl y one scs pi n. if t he m aster ne eds t o c ontrol multiple slave devices from a single master, the master can use i/o pin to select the slave devices. rev. 1.10 11 ? de?e??e? 1?? ?01? rev. 1.10 113 de ? e ?? e ? 1 ?? ? 01 ? HT45F75 body fat scale flash mcu HT45F75 body fat scale flash mcu ?? ? ? ? ? - ? ? ?? ? ? ?? ? ? ? spi block diagram spi interface operation the spi i nterface i s a f ull d uplex sy nchronous se rial d ata l ink. i t i s a f our l ine i nterface wi th p in names sdi, sdo, sck and scs . pins sdi and sdo are the serial data input and serial data output lines, sck is the serial clock line and scs is the slave select line. as the spi interface pins are pin- shared with normal i/o pins and with the i 2 c function pins, the spi interface must frst be enabled by setting the correct bits in the simc0 and simc2 registers. the spi can be disabled or enabled using the simen bit in the simc0 register . communication between devices connected to the spi interface is carried out in a slave/master mode with all data transfer initiations being implemented by the master . the master also controls the clock signal. as the devic e only contains a single scs pin only one slave device can be utilized. the scs pin is controlled by software, set csen bit to "1" to enable scs pin function, set csen bit to "0" the scs pin will be foating state. spi master/slave connection the spi function in this device offers the following features: ? full duplex synchronous data transfer ? both master and slave modes ? lsb frst or msb frst data transmission modes ? transmission complete fag ? rising or falling active clock edge the status of the spi interface pins is determined by a number of facto rs such as whether the device is in the master or slave mode and upon the condition of certain control bits such as csen and simen. rev. 1.10 11 ? de ? e ?? e ? 1 ?? ? 01 ? rev. 1.10 115 de?e??e? 1?? ?01? HT45F75 body fat scale flash mcu HT45F75 body fat scale flash mcu spi registers there are three internal registers which control the overall operation of the spi interface. these are the simd data register and two registers simc0 and simc2. note that the simc1 register is only used by the i 2 c interface. register name bit 7 6 5 4 3 2 1 0 simc0 sim ? sim1 sim0 simdbc1 simdbc0 simen simicf simd d7 d ? d5 d ? d3 d ? d1 d0 simc ? d7 d ? ckpolb ckeg mls csen wcol trf sim registers list the simd register is used to store the data being transmitted and received. the same register is used by both the spi and i 2 c functions. before the device writes data to the spi bus, the actual data to be transmitted must be placed in the simd register . after the data is received from the spi bus, the device can read it from the simd register . any transmission or reception of data from the spi bus must be made via the simd register. simd register bit 7 6 5 4 3 2 1 0 na ? e d7 d ? d5 d ? d3 d ? d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por x x x x x x x x x unknown there are also two control registers for the spi interface, simc0 and simc2. note that the simc2 register also has the name sima which is used by the i 2 c function. the simc1 register is not used by the spi functio n, only by the i 2 c function. register simc0 is used to control the enable/disable function a nd t o se t t he da ta t ransmission c lock fre quency. al though not c onnected wi th t he spi function, the simc0 register is also used to control the peripheral clock prescaler . register simc2 is used for other control functions such as lsb/msb selection, write collision fag etc. simc0 register bit 7 6 5 4 3 2 1 0 na ? e sim ? sim1 sim0 simdbc1 simdbc0 simen simicf r/w r/w r/w r/w r/w r/w r/w r/w por 1 1 1 0 0 0 0 bit 7~5 sim2~sim0 : sim operating mode control 000: spi master mode; spi clock is f /4 001: spi master mode; spi clock is f /16 010: spi master mode; spi clock is f /64 011: spi master mode; spi clock is f 100: spi master mode; spi clock is tm0 ccrp match frequency/2 101: spi slave mode 110: i 2 c slave mode 111: unused mode these bits setup the overall operatin g mode of the sim function. as well as selecting if t he i 2 c or spi func tion, t hey a re used t o c ontrol t he spi ma ster/slave sel ection and the spi master clock frequency . the spi clock is a function of the system clock but can also be chosen to be sourced from the f or tm0. if the spi slave mode is selected then the clock will be supplied by an external master device. bit 4 unimplemented, read as 0 rev. 1.10 11 ? de?e??e? 1?? ?01? rev. 1.10 115 de ? e ?? e ? 1 ?? ? 01 ? HT45F75 body fat scale flash mcu HT45F75 body fat scale flash mcu bit 3~2 simdbc1~simdbc0 : i 2 c debounce t ime selection 00: no debounce 01: 2 system clock debounce 1x: 4 system clock debounce bit 1 simen : sim control 0: disable 1: enable the bi t is the overa ll on/of f control for the sim interface. when the simen bi t is cleared to zero to disable the sim interface, the sdi, sdo, sck and scs , or sda and scl lines will be in a foating condition and the sim operating current will be reduced to a mini mum value. when the bit is high the sim interface is enabled. the sim confguration option must have frst enabled the sim interface for this bit to be effective. if the sim is confgured to operate as an spi interface via the sim2~sim0 bits, the contents of the spi control registers will remain at the previous settings when the simen bit changes from low to high and should therefore be frst initiali sed by the applic ation program. if the sim is confgured to operate as an i 2 c interface via the sim2~sim0 bits and the simen bit changes from low to high, the contents of the i 2 c control bits such as htx and txak will remain at the previous setti ngs and should therefore be first initialised by the application program while the relevant i 2 c flags such as hcf, haas, hbb, srw and rxak will be set to their default states. bit 0 simicf : sim incompleted flag 0: sim incompleted is not occurred 1: sim incompleted is occurred the simicf bit is determined by scs pin. when scs pin is set high, it will clear the spi counter. meanwhile, the interrupt is occurred and the incompleted fag, simicf, is set high. simc2 register bit 7 6 5 4 3 2 1 0 na ? e d7 d ? ckpolb ckeg mls csen wcol trf r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~6 d7~d6 : undefned bit this bit can be read or written by user software program. bit 5 ckpolb : determines the base condition of the clock line 0: the sck line will be high when the clock is inactive 1: the sck line will be low when the clock is inactive the ckpolb bi t determines the ba se condition of the clock line, if the bi t is hi gh, then t he sck l ine wi ll be l ow whe n t he c lock i s i nactive. w hen t he ckpol b bi t i s low, then the sck line will be high when the clock is inactive. bit 4 ckeg : determines spi sck active clock edge type ckpolb=0 0: sck is high base level and data capture at sck rising edge 1: sck is high base level and data capture at sck falling edge ckpolb=1 0: sck is low base level and data capture at sck falling edge 1: sck is low base level and data capture at sck rising edge the ckeg and ckpolb bits are used to setup the way that the clock signal outputs and inputs data on the spi bus. these two bits must be confgured before data transfer is e xecuted ot herwise a n e rroneous c lock e dge m ay be ge nerated. t he ckpol b bi t determines t he ba se c ondition of t he c lock l ine, i f t he bi t i s hi gh, t hen t he sck l ine will be low when the clock is inact ive. when the ckpolb bit is low , then the sck line will be high when the clock is inactive. the ckeg bit determines active clock edge type which depends upon the condition of ckpolb bit. rev. 1.10 11 ? de ? e ?? e ? 1 ?? ? 01 ? rev. 1.10 117 de?e??e? 1?? ?01? HT45F75 body fat scale flash mcu HT45F75 body fat scale flash mcu bit 3 mls : spi data shift order 0: lsb 1: msb this is the data shift select bit and is used to select how the data is transferred, either msb or lsb frst. setting the bit high will select msb frst and low for lsb frst. bit 2 csen : spi scs pin control 0: disable 1: enable the csen bit is used as an enable/disable for the scs pin. if this bit is low , then the scs pin will be disabled and placed into a foating condition. if the bit is high the scs pin will be enabled and used as a select pin. note that using the csen bit can be disabled or enabled via confguration option. bit 1 wcol : spi w rite collision fag 0: no collision 1: collision the wcol fag is used to detect if a data collision has occurred. if this bit is high it means that data has been attempted to be written to the simd register during a data transfer operation . this writing operation will be ignored if data is being transferred. the bit can be cle ared by the applic ation program. note that using the wcol bit can be disabled or enabled via confguration option. bit 0 trf : spi t ransmit/receive complete fag 0: data is being transferred 1: spi data transmission is completed the trf bit is the t ransmit/receive complete fag and is set high automatically when an spi da ta t ransmission i s c ompleted, but m ust c leared t o z ero by t he a pplication program. it can be used to generate an interrupt. spi communication after t he spi i nterface i s e nabled by se tting t he sime n bi t hi gh, t hen i n t he ma ster mode , whe n data is written to the simd register , transmission/reception will begin simultaneously . when the data t ransfer i s c omplete, t he t rf fl ag wi ll be se t a utomatically, but m ust be c leared usi ng t he application program. in the slave mode, when the clock signal from the master has been received, any data in the simd register will be transmitted and any data on the sdi pin will be shifted into the simd register . the master should output an scs signal to enable the slave device before a clock signal is provided. the slave data to be transferred should be well prepared at the appropriate moment relative to the scs signal depending upon the confgurations of the ckpolb bit and ckeg bit. the accompanying timing diagram shows the relationship between the slave data and scs signal for various confgurations of the ckpolb and ckeg bits. the spi will continue to function even in the idle mode. rev. 1.10 11 ? de?e??e? 1?? ?01? rev. 1.10 117 de ? e ?? e ? 1 ?? ? 01 ? HT45F75 body fat scale flash mcu HT45F75 body fat scale flash mcu ? ? ? ? ? ?? ?? ? ?? ? ?? ?? -? ?? ?? ?? ?? ?? -? ?? ? ?? ?? ? ?? ?? ?? ? ?? ? ?? ?? -? ?? ?? ?? ?? ?? -? ?? ? ?? ?? ? ?? ? ? ? spi master mode timing ? ? ? ? ??? ? - ? ? ?? spi slave mode timing ckeg=0 ? ? ?? ? ? ? ? ? ? ?? ?? ? - ? ?? ?? ? ? ?? ? ? ? ? ? ? ? ?? ?? ?? ? ? ? ? ?? ? ?? ? ?? ? ? ? ? ? ? ? ? spi slave mode timing ckeg=1 rev. 1.10 118 de ? e ?? e ? 1 ?? ? 01 ? rev. 1.10 119 de?e??e? 1?? ?01? HT45F75 body fat scale flash mcu HT45F75 body fat scale flash mcu ? ? ? ? ? ? ? ? ? ? ? -? ?? ? ? ? ? ? ? ???? ??? ? ????? ?? ?? ? ???? ? spi transfer control flowchart rev. 1.10 118 de?e??e? 1?? ?01? rev. 1.10 119 de ? e ?? e ? 1 ?? ? 01 ? HT45F75 body fat scale flash mcu HT45F75 body fat scale flash mcu i 2 c interface the i 2 c i nterface i s use d t o c ommunicate wi th e xternal pe ripheral de vices suc h a s se nsors e tc. originally de veloped by phi lips, i t i s a t wo l ine l ow spe ed se rial i nterface for sync hronous se rial data transfer . the advantage of only two lines for communication, relatively simple communication protocol and the ability to accommodate multiple devices on the same bus has made it an extremely popular interface type for many applications. i 2 c master/slave bus connection ? ? ? ? ??- ? ? ? ? ?? ? ? ? - ? ? ? ? ? ? ? ? ? ? ? ? ?? ? ?? ? i 2 c block diagram i 2 c interface operation the i 2 c serial interface is a two line interf ace, a serial data line, sda, and serial clock line, scl. as many devices may be connected together on the same bus, their outputs are both open drain types. for this reason it is necessary that external pull-high resistors are connected to these outputs. note that no chip select line exists, as each device on the i 2 c bus is identifed by a unique address which will be transmitted and received on the i 2 c bus. when two device s communicate with each other on the bidirectional i 2 c bus, one is known as the master de vice a nd one a s t he sl ave de vice. bot h m aster a nd sl ave c an t ransmit a nd re ceive da ta, however, i t i s t he m aster de vice t hat ha s ove rall c ontrol of t he bus. for t his de vice, wh ich onl y operates in slave mode, there are two methods of transferring data on the i 2 c bus, the slave transmit mode and the slave receive mode. the pull-up control function pin-shared with scl/sda pin is still applicable even if i 2 c device is activ ated and the related internal pull-up register could be controlled by its corresponding pull-up control register. rev. 1.10 1 ? 0 de ? e ?? e ? 1 ?? ? 01 ? rev. 1.10 1?1 de?e??e? 1?? ?01? HT45F75 body fat scale flash mcu HT45F75 body fat scale flash mcu i 2 c registers there a re t hree c ontrol re gisters a ssociated wi th t he i 2 c bus, simc0, simc1 a nd simt oc, one address register , sima and one data register , simd. the simd register , which is shown in the above spi section, is used to store the data being transmitted and received on the i 2 c bus. before the micro controller writes data to the i 2 c bus, the actual data to be transmitted must be placed in the simd register . after the data is received from the i 2 c bus, the microcontroller can read it from the simd register . any transmission or reception of data from the i 2 c bus must be made via the simd register. note that the sima registe r also has the name simc2 which is used by the spi function. bit simen and bits sim2~sim0 in register simc0 are used by the i 2 c interface. the simt oc register is used for i 2 c time-out control. register name bit 7 6 5 4 3 2 1 0 simc0 sim ? sim1 sim0 simdbc1 simdbc0 simen simicf simc1 hcf haas hbb htx txak srw rnic rxak simd d7 d ? d5 d ? d3 d ? d1 d0 sima iica ? iica5 iica ? iica3 iica ? iica1 iica0 d0 simtoc simtoen simtof simtos5 simtos ? simtos3 simtos ? simtos1 simtos0 i 2 c registers list rev. 1.10 1?0 de?e??e? 1?? ?01? rev. 1.10 1 ? 1 de ? e ?? e ? 1 ?? ? 01 ? HT45F75 body fat scale flash mcu HT45F75 body fat scale flash mcu simc0 register bit 7 6 5 4 3 2 1 0 na ? e sim ? sim1 sim0 simdbc1 simdbc0 simen simicf r/w r/w r/w r/w r/w r/w r/w r/w por 1 1 1 0 0 0 0 bit 7~5 sim2~sim0 : sim operating mode control 000: spi master mode; spi clock is f /4 001: spi master mode; spi clock is f /16 010: spi master mode; spi clock is f /64 011: spi master mode; spi clock is f 100: spi master mode; spi clock is tm0 ccrp match frequency/2 101: spi slave mode 110: i 2 c slave mode 111: unused mode these bits setup the overall operatin g mode of the sim function. as well as selecting if t he i 2 c or spi func tion, t hey a re used t o c ontrol t he spi ma ster/slave sel ection and the spi master clock frequency . the spi clock is a function of the system clock but can also be chosen to be sourced from the f or tm0. if the spi slave mode is selected then the clock will be supplied by an external master device. bit 4 unimplemented, read as 0 bit 3~2 simdbc1~simdbc0 : i 2 c debounce t ime selection 00: no debounce 01: 2 system clock debounce 1x: 4 system clock debounce bit 1 simen : sim control 0: disable 1: enable the bi t is the overa ll on/of f control for the sim interface. when the simen bi t is cleared to zero to disable the sim interface, the sdi, sdo, sck and scs , or sda and scl lines will be in a foating condition and the sim operating current will be reduced to a mini mum value. when the bit is high the sim interface is enabled. the sim confguration option must have frst enabled the sim interface for this bit to be effective. if the sim is confgured to operate as an spi interface via the sim2~sim0 bits, the contents of the spi control registers will remain at the previous settings when the simen bit changes from low to high and should therefore be frst initiali sed by the applic ation program. if the sim is confgured to operate as an i 2 c interface via the sim2~sim0 bits and the simen bit changes from low to high, the contents of the i 2 c control bits such as htx and txak will remain at the previous setti ngs and should therefore be first initialised by the application program while the relevant i 2 c flags such as hcf, haas, hbb, srw and rxak will be set to their default states. bit 0 simicf : sim incompleted flag simicf is of no used in i 2 c mode of sim, please ignore this fag when operate in i 2 c mode. rev. 1.10 1 ?? de ? e ?? e ? 1 ?? ? 01 ? rev. 1.10 1?3 de?e??e? 1?? ?01? HT45F75 body fat scale flash mcu HT45F75 body fat scale flash mcu simc1 register bit 7 6 5 4 3 2 1 0 na ? e hcf haas hbb htx txak srw rnic rxak r/w r r r r/w r/w r r/w r por 1 0 0 0 0 0 0 1 bit 7 hcf : i 2 c bus data transfer completion fag 0: data is being transferred 1: completion of an 8-bit data transfer the hcf flag is the data transfer flag. this flag will be zero when data is being transferred. upon completion of an 8-bit data transfer the flag will go high and an interrupt will be generated. bit 6 haas : i 2 c bus address match fag 0: not address match 1: address match the hass fag i s t he a ddress m atch fag. t his fag i s used t o de termine i f t he sla ve device address is the same as the master transmit address. if the addresses match then this bit will be high, if there is no match then the fag will be low. bit 5 hbb : i 2 c bus busy fag 0: i 2 c bus is not busy 1: i 2 c bus is busy the hbb flag is the i 2 c busy flag. this flag will be 1 when the i 2 c bus is busy which will occur when a st art signal is detected. the fag will be cleared to zero when the bus is free which will occur when a stop signal is detected. bit 4 htx : select i 2 c slave device is transmitter or receiver 0: slave device is the receiver 1: slave device is the transmitter bit 3 txak : i 2 c bus transmit acknowledge fag 0: slave send acknowledge fag 1: slave do not send acknowledge fag the txak bit is the transmit acknowledge fag. after the slave device receipt of 8-bits of data, this bit will be transmitted to the bus on the 9th clock from the slave device. the slave device must always set txak bit to "0" before further data is received. bit 2 srw : i 2 c slave read/write fag 0: slave device should be in receive mode 1: slave device should be in transmit mode the sr w f lag i s t he i 2 c sl ave r ead/write f lag. t his f lag d etermines wh ether the master device wishes to transmit or receive data from the i 2 c bus. when the transmitted address and slave address is match, that is when the haas fag is set high, the slave device will check the sr w fag to determine whether it should be in transmit mode or receive mode. if the sr w fag is high, the master is requesting to read data from the bus, so the slave device should be in transmit mode. when the sr w flag is zero, the master will write data to the bus, therefore the slave device should be in receive mode to read this data. bit 1 rnic : i 2 c running not using internal clock. 0: i 2 c running using internal clock 1: i 2 c running not using internal clock the i 2 c module can run without using internal clock, and generate an interr upt if the sim interrupt is enabled, which can be used in sleep mode, idle (slow) mode and normal (slow) mode. note: if rnic=1 and mcu is in halt, slave-receiver can work well but slave- transmitter doesnt work since it needs system clock. rev. 1.10 1?? de?e??e? 1?? ?01? rev. 1.10 1 ? 3 de ? e ?? e ? 1 ?? ? 01 ? HT45F75 body fat scale flash mcu HT45F75 body fat scale flash mcu bit 0 rxak : i 2 c bus receive acknowledge fag 0: slave receive acknowledge fag 1: slave do not receive acknowledge fag the simd register is used to store the data being transmitted and received. the same register is used by bot h t he spi a nd i 2 c fun ctions. be fore t he de vice wri tes da ta t o t he i 2 c bus, t he a ctual da ta t o be transmitted must be placed in the simd register . after the data is received from the i 2 c bus, the device can read it from the simd register . any transmission or reception of data from the i 2 c bus must be made via the simd register. simd register bit 7 6 5 4 3 2 1 0 na ? e d7 d ? d5 d ? d3 d ? d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por x x x x x x x x x unknown sima register bit 7 6 5 4 3 2 1 0 na ? e iica ? iica5 iica ? iica3 iica ? iica1 iica0 d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~1 iica6~iica0 : i 2 c slave address iica6~ iica0 is the i 2 c slave address bit 6 ~ bit 0. the si ma r egister i s a lso u sed b y t he spi i nterface b ut h as t he n ame si mc2. t he sima register is the location where the 7-bit slave address of the slave device is stored. bits 7~ 1 of the sima register define the device slave address. bit 0 is not defned. when a master device, which is connected to the i 2 c bus, sends out an address, which matches the slave address in the sima register , the slave device will be selected. note that the sima register is the same register address as simc2 which is used by the spi interface. bit 0 undefned bit this bit can be read or written by user software program. rev. 1.10 1 ?? de ? e ?? e ? 1 ?? ? 01 ? rev. 1.10 1?5 de?e??e? 1?? ?01? HT45F75 body fat scale flash mcu HT45F75 body fat scale flash mcu simtoc register bit 7 6 5 4 3 2 1 0 na ? e simtoen simtof simtos5 simtos ? simtos3 simtos ? simtos1 simtos0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7 simtoen : i 2 c interface t ime-out control 0: disable 1: enable bit 6 simtof : i 2 c interface t ime-out fag 0: no occurred 1: occurred the simt of fag is set by the time-out circuitry when the time-out event occurs and cleared by software program. bit 5~0 simtos5~simtos0 : i 2 c interface t ime-out period selection the i 2 c t ime-out clock source is f /32. the i 2 c t ime-out time is ([simtos5:simtos0] + 1) (32/f ) i 2 c bus communication communication on the i 2 c bus requires four separate steps, a st art signal, a slave device address transmission, a data transmission and finally a st op signal. when a st art signal is placed on the i 2 c bus, all devices on the bus will receive this signal and be notifed of the imminent arrival of data on the bus. the frst seven bits of the data will be the slave address with the frst bit being the msb. if the address of the slave device matches that of the transmitted address, the haas bit in the simc1 register will be set and an i 2 c interrupt will be generated. after entering the interrupt service routine, the slave device must frst check the condition of the haas bit to determine whether the interrupt source originates from an address match or from the comple tion of an 8-bit data transfer . during a data transfer , note that after the 7-bit slave address has been transmitted, the following bit, which is the 8th bit, is the read/writ e bit whose value will be placed in the sr w bit. this bit will be checked by the slave device to determine whether to go into transmit or receive mode. before any transfer of data to or from the i 2 c bus, the microcontroller must init ialise the bus, the following are steps to achieve this: ? step 1 set the sim2~sim0 bits to "1 10" and the simen bits to "1" in the simc0 register to enable the 2 c bus. ? step 2 write the slave address of the device to the i 2 c bus address register sima. ? step 3 set the sie and sim muti-function interrupt enable bit of the interrupt control register to enable the sim interrupt and multi-function interrupt. rev. 1.10 1?? de?e??e? 1?? ?01? rev. 1.10 1 ? 5 de ? e ?? e ? 1 ?? ? 01 ? HT45F75 body fat scale flash mcu HT45F75 body fat scale flash mcu ? ? ? ? ? ? - ? ? ? ?? ? ? ? ? ? - i 2 c bus initialisation flow chart i 2 c bus start signal the st art signal can only be generated by the master device connec ted to the i 2 c bus and not by the slave device. this st art signal will be detected by all devices connected to the i 2 c bus. when detected, this indicates that the i 2 c bus is busy and therefore the hbb bit will be set. a st art condition occurs when a high to low transition on the sda line takes place when the scl line remains high. slave address the t ransmission o f a st art si gnal b y t he m aster wi ll b e d etected b y a ll d evices o n t he i 2 c b us. to determine which slave device the master wishes to communicate with, the address of the slave device will be sent out immediately following the st art signal. all slave devices, after receiving this 7-bit address data, will compare it with their own 7-bit slave address. if the address sent out by the maste r matche s the internal address of the microcontroller slave device, then an internal i 2 c bus interrupt signal wil l be generat ed. the next bit fol lowing the address, which is the 8th bit, defnes the read/write status and will be saved to the sr w bit of the simc1 register . the slave device will then transmit an acknowledge bit, which is a low level, as the 9th bit. the slave device will also set the status fag haas when the addresses match. as an i 2 c bus interrupt can come from two sources, when the program enters the interrupt subroutine, t he haas bi t shoul d be e xamined t o se e whe ther t he i nterrupt sourc e ha s c ome from a matching slave address or from the completion of a data byte transfer . when a slave address is matched, the device must be placed in either the transmit mode and then w rite data to the s imd register, or in the receive mode where it must implement a dummy read from the simd register to release the scl line. i 2 c bus read/write signal the sr w bit in the simc1 registe r defnes whether the slave device wishes to read data from the i 2 c bus or write data to the i 2 c bus. the slave device should examine this bit to determine if it is to be a transmitter or a receiver . if the sr w fag is 1 then this indicates that the master device wishes to read data from the i 2 c bus, therefore the slave device must be setup to send data to the i 2 c bus as a transmitter . if the sr w fag is 0 then this indicates that the master wishes to send data to the i 2 c bus, therefore the slave device must be setup to read data from the i 2 c bus as a receiver. rev. 1.10 1 ?? de ? e ?? e ? 1 ?? ? 01 ? rev. 1.10 1?7 de?e??e? 1?? ?01? HT45F75 body fat scale flash mcu HT45F75 body fat scale flash mcu i 2 c bus slave address acknowledge signal after the mas ter has trans mitted a calling addres s, any s lave device on the i 2 c bus , w hose own internal address matches the calling address, must generate an acknowledge signal. the acknowledge signal will inform the master that a slave device has accepted its calling address. if no acknowledge signal is received by the master then a st op signal must be transmitted by the master to end the communication. when the haas fag is high, the addresses have matched and the slave device must check the sr w fag to determine if it is to be a transmitter or a receiver . if the sr w fag is high, the slave device should be setup to be a transmitter so the htx bit in the simc1 register should be set high. if the sr w fag is low , then the microcontroller slave device should be setup as a receiver and the htx bit in the simc1 register should be cleared to zero. i 2 c bus data and acknowledge signal the transmitted data is 8-bits wide and is transmitted after the slave device has acknowledged receipt o f i ts sl ave a ddress. t he o rder o f se rial b it t ransmission i s t he msb fr st a nd t he l sb l ast. after receipt of 8-bits of data, the receiver must transmit an acknowle dge signal, level 0, before it can receive the next data byte. if the slave transmitter does not recei ve an acknowledge bit signal from the master receiver , then the slave transmitter will release the sda line to allow the master to send a st op signal to release the i 2 c bus. the corresponding data will be stored in the simd register. if setup as a transmitter , the slave device must frst write the data to be transmitted into the simd register . if setup as a receive r, the slave device must read the transmitted data from the simd register. when the slave receiver receives the data byte, it must generate an acknowledge bit, known as txak, on the 9th clock. the slave device, which is setup as a transmi tter will check the rxak bit in the simc1 register to determine if it is to send another data byte, if not then it will release the sda line and await the receipt of a stop signal from the master. ? ? ? ? ? ? ? ? - ? - ? ? i 2 c communication timing diagram note: *when a slave address is matched, the device must be placed in either the transmit mode and then write data to the simd register , or in the receive mode where it must implement a dummy read from the simd register to release the scl line. rev. 1.10 1?? de?e??e? 1?? ?01? rev. 1.10 1 ? 7 de ? e ?? e ? 1 ?? ? 01 ? HT45F75 body fat scale flash mcu HT45F75 body fat scale flash mcu ? ? ? ? i 2 c bus isr flow chart i 2 c time out function in order to reduce the i 2 c lockup problem due to reception of erroneous clock sources , a time-out function is provided. if the clock source connected to the i 2 c bus is not received for a while, then the i 2 c circuitry and the simc1 register will be reset, the simt of bit in the simt oc register will be set high after a certain time-out period. the t ime out function enable/disable and the time-out period are managed by the simtoc register. rev. 1.10 1 ? 8 de ? e ?? e ? 1 ?? ? 01 ? rev. 1.10 1?9 de?e??e? 1?? ?01? HT45F75 body fat scale flash mcu HT45F75 body fat scale flash mcu i 2 c time out operation the t ime-out c ounter st arts t o c ount o n a n i 2 c b us start & address m atch condition, a nd is c leared b y a n sc l f alling e dge. b efore t he n ext sc l f alling e dge a rrives, i f t he t ime e lapsed i s greater t han t he t ime-out p eriod sp ecifed b y t he si mtoc r egister, t hen a t ime-out c ondition wi ll occur. the time-ou t function will stop when an i 2 c st op condition occurs. there are 64 time-out period selections which can be selected using the simtos0~simtos5 bits in the simtoc register. i 2 c time-out diagram when an i 2 c time-out counter overfow occurs, the counter will stop and the simt oen bit will be c leared t o z ero a nd t he simt of bi t wi ll be se t hi gh t o i ndicate t hat a t ime-out c ondition ha s occurred. the tim e-out condition will also generate an interrupt. when an i 2 c time-out occurs, the i 2 c internal circuitry will be reset and the registers will be reset into the following condition: register after i 2 c time-out simd ? sima ? simc0 no ? hange simc1 reset to por ? ondition i 2 c registers after time-out rev. 1.10 1?8 de?e??e? 1?? ?01? rev. 1.10 1 ? 9 de ? e ?? e ? 1 ?? ? 01 ? HT45F75 body fat scale flash mcu HT45F75 body fat scale flash mcu uart module serial interface with ir carrier uart module features ? full-duplex, universal asynchronous receiver and t ransmitter (uart) communication ? 8 or 9 bits character length ? even, odd or no parity options ? one or two stop bits ? baud rate generator with 8-bit prescaler ? parity, framing, noise and overrun error detection ? support for interrupt on address detect (last character bit=1) ? transmitter and receiver enabled independently ? 2-byte deep fifo receive data buffer ? transmit and receive multiple interrupt generation sources: ? transmitter empty ? transmitter idle ? receiver full ? receiver overrun ? address mode detect uart module overview the embedded uar t module is full-duplex asynchronous serial communications uar t interface that enables communication with external devices that contain a serial interface. the uart function has many features and can transmit and receive data serially by transferring a frame of data with eight or nine data bits per transmission as well as being able to detect errors when the data is overwritten or incorrectly framed. the uar t function possesses its own internal interrupt which can be used to indicate when a reception occurs or when a transmission terminates. uart external pin interfacing to communicate with an external serial interface, the internal uar t has two external pins known as tx and rx. the tx pin is the uar t transmitter pin, which can be used as a general purpose i/o or other pin-shared functional pin if the pin is not confgured as a uar t transmitter , which occurs when the txen bit in the ucr2 control register is equal to zero. simil arly, the rx pin is the uar t receiver pin, which can also be used as a general purpose i/o or other pin-shared functional pin, if the pin is not confgured as a receiver , which occurs if the rxen bit in the ucr2 register is equal to zero. along with the uar ten bit, the txen and rxen bits, if set, will automatically setup these i/o or other pin-shared functional pins to their respective tx output and rx input conditions and disable any pull-high resistor option which may exist on the rx pin. uart data transfer scheme the block diagram shows the overall data transfer structure arrangement for the uar t. the actual data t o be t ransmitted from t he mcu i s fi rst t ransferred t o t he t xr re gister by t he a pplication program. the data will then be transferred to the t ransmit shift register from where it will be shifted o ut, l sb fr st, o nto t he t x p in a t a r ate c ontrolled b y t he b aud r ate ge nerator. on ly t he txr register is mapped onto the mcu data memory , the t ransmit shift register is not mapped and is therefore inaccessible to the application program. rev. 1.10 130 de ? e ?? e ? 1 ?? ? 01 ? rev. 1.10 131 de?e??e? 1?? ?01? HT45F75 body fat scale flash mcu HT45F75 body fat scale flash mcu data to be received by the uar t is accepted on the external rx pin, from where it is shifted in, lsb fi rst, t o t he re ceiver shi ft r egister a t a ra te c ontrolled by t he b aud ra te ge nerator. w hen the shift register is full, the data will then be transferred from the shift register to the internal rxr register, where it is buf fered and can be manipulated by the application program. only the rxr register i s m apped ont o t he mcu da ta me mory, t he re ceiver shift re gister i s not m apped a nd i s therefore inaccessible to the application program. it should be noted that the actual register for data transmission and reception, although referred to in the text, and in application programs, as separate txr and rxr registers, only exists as a single shared register in the data memory . this shared register known as the txrrxr register is used for both data transmission and data reception. msb lsb t?ans?itte? shift registe? (tsr) msb lsb re?eive? shift registe? (rsr) tx pin rx pin baud rate gene?ato? tx registe? (txr) rx registe? (rxr) data to ?e t?ans?itted data ?e?eived buffe? f sys mcu data bus uart data transfer scheme uart status and control registers there are fve control registers associated with the uar t function. the usr, ucr1 and ucr2 registers control the overall function of the u art, w hile the brg regis ter controls the baud rate. the actual data to be transmitted and received on the serial interface is managed through the txrrxr data register. register name bit 7 6 5 4 3 2 1 0 usr perr nf ferr oerr ridle rxif tidle txif ucr1 uarten bno pren prt stops txbrk rx8 tx8 ucr ? txen rxen brgh adden wake rie tiie teie txrrxr txrxd7 txrxd ? txrxd5 txrxd ? txrxd3 txrxd ? txrxd1 txrxd0 brg brgd7 brgd ? brgd5 brgd ? brgd3 brgd ? brgd1 brgd0 uart register summary usr register the usr register is the status register for the uart, which can be read by the program to determine the present status of the uar t. all fags within the usr register are read only . further explanation on each of the fags is given below: bit 7 6 5 4 3 2 1 0 na ? e perr nf ferr oerr ridle rxif tidle txif r/w r r r r r r r r por 0 0 0 0 1 0 1 1 bit 7 perr : parity error fag 0: no parity error is detected 1: parity error is detected rev. 1.10 130 de?e??e? 1?? ?01? rev. 1.10 131 de ? e ?? e ? 1 ?? ? 01 ? HT45F75 body fat scale flash mcu HT45F75 body fat scale flash mcu the perr fag is the parity error fag. when this read only fag is "0", it indicates a parity error has not been detected. when the fag is "1", it indicates that the parity of the received word is incorrect. this error fag is applicable only if parity mode (odd or even) is selected. the fag can also be cleared by a software sequence which involves a read to the status register usr followed by an access to the rxr data register. bit 6 nf : noise fag 0: no noise is detected 1: noise is detected the nf fla g is the noise fla g. whe n thi s read only fla g is "0", it indi cates no noise condition. when the fag is "1", it indicates that the uar t has detected noise on the receiver input. the nf fag is set during the same cycle as the rxif fag but will not be set in the case of as overrun. the n f fag can be cleared by a softw are sequence which will involve a read to the status register usr followed by an access to the rxr data register. bit 5 ferr : framing error fag 0: no framing error is detected 1: framing error is detected the ferr fag is the framing error fag. when this read only fag is "0", it indicates that there is no framing error . when the fag is " 1", it indicates that a framing error has been detected for the current character . the fag can also be cleared by a software sequence which will involve a read to the status register usr followed by an access to the rxr data register. bit 4 oerr : overrun error fag 0: no overrun error is detected 1: overrun error is detected the oerr fag is the overrun error fag which indicates when the rece iver buf fer has overfowed. when this read only fag is "0", it indicates that there is no overrun error . when the fag is "1", it indicates that an overrun error occurs which will inhibit further transfers to the rxr receive data register . the fag is cleared by a software sequence, which is a read to the s tatus regis ter u sr follow ed by an acces s to the rx r data register. bit 3 ridle : receiver status 0: data reception is in progress (data being received) 1: no data reception is in progress (receiver is idle) the ridle fag is the receiver status fag. when this read only fag is "0", it indicates that the receiver is between the init ial detection of the start bit and the completion of the stop bit. when the fag is "1", it indicates that the receiver is idle. between the completion of the stop bit and the detection of the next start bit, the ridle bit is "1" indicating that the uart receiver is idle and the rx pin stays in logic high condition. bit 2 rxif : receive rxr data register status 0: rxr data register is empty 1: rxr data register has available data the rxif fag is the receive data register status fag. when this read only fag is "0", it indicates that the rxr read data register is empty . when the fag is "1", it indicates that t he r xr r ead d ata r egister c ontains n ew d ata. w hen t he c ontents o f t he sh ift register are trans ferred to the rx r register , an interrupt is generated if rie=1 in the ucr2 register . if one or more errors are detected in the received word, the appropriate receive-related fags nf , ferr, and/or perr are set within the same clock cycle. the rxif fag is clear ed when the usr register is read with rxif set, followed by a read from the rxr register, and if the rxr register has no data available. bit 1 tidle : t ransmission idle 0: data transmission is in progress (data being transmitted) 1: no data transmission is in progress (transmitter is idle) rev. 1.10 13 ? de ? e ?? e ? 1 ?? ? 01 ? rev. 1.10 133 de?e??e? 1?? ?01? HT45F75 body fat scale flash mcu HT45F75 body fat scale flash mcu the tidle flag is known as the transmission complete flag. when this read only flag is " 0", it indicates that a transmiss ion is in progress. this flag will be set high when the txif fag is "1" and when there is no transmit data or break character being transmitted. when tidle is equal to "1", the tx pin becomes idle with the pin state in logic high condition. the tidle fag is cleared by reading the usr register with tidle set and then writing to the txr register . the fag is not generated when a data character or a break is queued and ready to be sent. bit 0 txif : t ransmit txr data register status 0: character is not transferred to the transmit shift register 1: character has transferred to the transmit shift register (txr data register is empty) the txif fag is the transmit data register empty fag. when this read only fag is "0", it indicat es that the character is not transferred to the transmitter shift register . when the fag is "1", it indicates that the transmitter shift register has received a character from the txr data register . the txif flag is cleared by reading the uar t status register (usr) with txif set and then writing to the txr data register . note that when t he t xen b it i s se t, t he t xif fa g b it wi ll a lso b e se t si nce t he t ransmit d ata register is not yet full. ucr1 register the ucr1 register together with the ucr2 register are the two uart control registers that are used to set the various options for the uar t function, such as overall on/of f control, parity control, data transfer bit length etc. further explanation on each of the bits is given below: bit 7 6 5 4 3 2 1 0 na ? e uarten bno pren prt stops txbrk rx8 tx8 r/w r/w r/w r/w r/w r/w r/w r w por 0 0 0 0 0 0 x 0 x unknown bit 7 uarten : uart function enable control 0: disable uart. tx and rx pins are used as i/o or other pin-shared functional pins 1: enable uart. tx and rx pins function as uart pins the uar ten bit is the uar t enable bit. when this bit is equal to "0", the uar t will be disabled and the rx pin as well as the tx pin will be as general purpose i/o or other pin-shared functional pins. when the bit is equal to 1, the uar t will be enabled and the tx and rx pins will function as defned by the txen and rxen enable control bits. when the uar t is disabled, it will empty the buf fer so any character remaining in the buf fer will be discarded. in addition, the value of the baud rate counter will be reset. if the uar t is disabled, all error and status fags will be reset. also the txen, rxen, txbrk, rxif , oerr, ferr, perr and nf bits will be cle ared, while the tidle, txif and ridle bits will be set. other control bits in ucr1, ucr2 and brg registers will remain unaf fected. if the uar t is active and the uar ten bit is cleared, all pending transmis sions and receptions will be terminated and the module will be reset as defined above. when the uar t is re-enabled, it will restart in the same confguration. bit 6 bno : number of data transfer bits selection 0: 8-bit data transfer 1: 9-bit data transfer this bit is used to select the data length format, which can have a choice of either 8-bit or 9-bit format. when this bit is equal to "1", a 9-bit data length format will be selected. if the bit is equal to "0", then an 8-bit data length format will be selected. if 9-bit data length format is selected, then bits rx8 and tx8 will be used to store the 9th bit of the received and transmitted data respectively. rev. 1.10 13? de?e??e? 1?? ?01? rev. 1.10 133 de ? e ?? e ? 1 ?? ? 01 ? HT45F75 body fat scale flash mcu HT45F75 body fat scale flash mcu bit 5 pren : parity function enable control 0: parity function is disabled 1: parity function is enabled this is the parity enable bit. when this bit is equal to "1", the parity function will be enabled. if the bit is equal to "0", then the parity function will be disabled. replace the most signifcant bit position with a parity bit. bit 4 prt : parity type selection bit 0: even parity for parity generator 1: odd parity for parity generator this bit is the parity type selection bit. when this bit is equal to "1", odd parity type will be selected. if the bit is equal to "0", then even parity type will be selected. bit 3 stops : number of stop bits selection 0: one stop bit format is used 1: t wo stop bits format is used this bit determines if one or two stop bits are to be used. when this bit is equal to "1", two stop bits are used. if this bit is equal to "0", then only one stop bit is used. bit 2 txbrk : t ransmit break character 0: no break character is transmitted 1: break characters transmit the txbrk bit is the t ransmit break character bit. when this bit is "0", there are no break characte rs and the tx pin operates normally . when the bit is "1", there are transmit break characters and the transmitter will send logic zeros. when this bit is equal to "1", after the buf fered data has been transmitted, the transmitter output is held low for a minimum of a 13-bit length and until the txbrk bit is reset. bit 1 rx8 : receive data bit 8 for 9-bit data transfer format (read only) this bit is only used if 9-bit data transfers are used, in which case this bit location will store the 9th bit of the received data known as rx8. the bno bit is used to determine whether data transfers are in 8-bit or 9-bit format. bit 0 tx8 : t ransmit data bit 8 for 9-bit data transfer format (write only) this bit is only us ed if 9-bit data transfers are us ed, in w hich cas e this bit location will st ore t he 9 th b it o f t he t ransmitted d ata k nown a s t x8. t he b no b it i s u sed t o determine whether data transfers are in 8-bit or 9-bit format. ucr2 register the ucr2 register is the second of the two uart control registers and serves several purposes. one of its main functio ns is to control the basic enable/disable operation of the uar t t ransmitter and receiver as well as enabling the various uar t interrupt sources. the register also serves to control the baud rate speed, receiver wake-up enable and the address detect enable. further explanation on each of the bits is given below: bit 7 6 5 4 3 2 1 0 na ? e txen rxen brgh adden wake rie tiie teie r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7 txen : uart t ransmitter enabled control 0: uart transmitter is disabled 1: uart transmitter is enabled the bit named txen is the t ransmitter enable bit. when this bit is equal to "0", the transmitter will be disabled with any pending data transmissions being aborted. in addition the buf fers will be reset. in this situation the tx pin will be used as an i/o or other pin-shared functional pin. rev. 1.10 13 ? de ? e ?? e ? 1 ?? ? 01 ? rev. 1.10 135 de?e??e? 1?? ?01? HT45F75 body fat scale flash mcu HT45F75 body fat scale flash mcu if the txen bit is equal to "1" and the uar ten bit is also equal to "1", the transmitter will be enabled and the tx pin will be controlled by the uar t. clearing the txen bit during a transmission will cause the data transmission to be aborted and will reset the transmitter . if this situation occurs, the tx pin will be used as an i/o or other pin-shared functional pin. bit 6 rxen : uart receiver enabled control 0: uart receiver is disabled 1: uart receiver is enabled the bi t na med rxe n i s t he re ceiver e nable bi t. w hen t his bi t i s e qual t o "0", t he receiver will be disabled with any pending data receptions being aborted. in addition the receive buf fers will be reset. in this situation the rx pin will be used as an i/o or other pin-shared functional pin. if the rxen bit is equal to "1" and the uar ten bit is also equal to "1", the receiver will be enabled and the rx pin will be controlled by the uar t. cleari ng the rxen bit during a reception will cause the data reception to be aborted and will reset the receiv er. if this situation occurs, the rx pin will be used as an i/o or other pin-shared functional pin. bit 5 brgh : baud rate speed selection 0: low speed baud rate 1: high speed baud rate the bit named brgh selects the high or low speed mode of the baud rate generator . this bit, together with the value placed in the baud rate register brg, controls the baud rate of the uar t. if this bit is equal to "1", the high speed mode is selected. if the bit is equal to "0", the low speed mode is selected. bit 4 adden : address detect function enable control 0: address detect function is disabled 1: address detect function is enabled the bi t na med adde n i s t he a ddress de tect fu nction e nable c ontrol bi t. w hen t his bit i s e qual t o "1", t he a ddress de tect func tion i s e nabled. w hen i t oc curs, i f t he 8t h bit, which corresponds to rx7 if bno=0 or the 9th bit, which corresponds to rx8 if bno=1, ha s a va lue of "1 ", t hen t he re ceived word wi ll be i dentifed a s a n a ddress, rather than data. if the corresponding interrupt is enabled, an interrupt request will be generated each time the received word has the address bit set, which is the 8th or 9th bit d epending o n t he v alue o f b no. i f t he a ddress b it k nown a s t he 8 th o r 9 th b it o f t he received word is "0" with the address detect function being enabled, an interrupt will not be generated and the received data will be discarded. bit 3 wake : rx pin falling edge wake-up function enable control 0: rx pin wake-up function is disabled 1: rx pin wake-up function is enabled the bit enables or disables the rece iver wake-up function. if this bit is equal to 1 and the device is in idle0 or sleep mode, a falling edge on the rx pin will wake up the device. if this bit is equal to 0 and the device is in idle or sleep mode, any edge transitions on the rx pin will not wake up the device. bit 2 rie : receiver interrupt enable control 0: receiver related interrupt is disabled 1: receiver related interrupt is enabled this bit enables or disables the rece iver interrupt. if this bit is equal to "1" and when the receiver overrun fag oerr or receive data available fag rxif is set, the uar t interrupt request fag will be set. if this bit is equal to "0", the uar t interrupt request fag will not be infuenced by the condition of the oerr or rxif fags. bit 1 tiie : t ransmitter idle interrupt enable control 0: t ransmitter idle interrupt is disabled 1: t ransmitter idle interrupt is enabled this bit enables or disables the transmitter idle interrupt. if this bit is equal to "1" and when t he t ransmitter i dle fa g t idle i s se t, due t o a t ransmitter i dle c ondition, t he uart interrupt request fag will be set. if this bit is equal to "0", the uar t interrupt request fag will not be infuenced by the condition of the tidle fag. rev. 1.10 13? de?e??e? 1?? ?01? rev. 1.10 135 de ? e ?? e ? 1 ?? ? 01 ? HT45F75 body fat scale flash mcu HT45F75 body fat scale flash mcu bit 0 teie : t ransmitter empty interrupt enable control 0: t ransmitter empty interrupt is disabled 1: t ransmitter empty interrupt is enabled this bit enables or disables the transmitter empty interrupt. if this bit is equal to "1" and when the transmitter empty fag txif is set, due to a transmitter empty condition, the uar t i nterrupt re quest fl ag wi ll be se t. if t his bi t i s e qual t o "0", t he uar t interrupt request fag will not be infuenced by the condition of the txif fag. txrrxr register bit 7 6 5 4 3 2 1 0 na ? e txrxd7 txrxd ? txrxd5 txrxd ? txrxd3 txrxd ? txrxd1 txrxd0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por x x x x x x x x x unknown bit 7~0 txrxd7~txrxd0 : uart t ransmit/receive data bit 7 ~ bit 0 brg register bit 7 6 5 4 3 2 1 0 na ? e brgd7 brgd ? brgd5 brgd ? brgd3 brgd ? brgd1 brgd0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por x x x x x x x x x unknown bit 7~0 brgd7~brgd0 : baud rate values by programming the brgh bit in ucr2 register which allows selection of the related formula described above and programming the required value in the brg register, the required baud rate can be setup. note: baud rate= f /[64(n+1)] if brgh=0. baud rate= f /[16(n+1)] if brgh=1. baud rate generator to setup the speed of the serial data communication, the uar t function contains its own dedicated baud ra te ge nerator. t he ba ud ra te i s c ontrolled by i ts own i nternal fre e runni ng 8-bi t t imer, t he period of which is determined by two factors. the frst of these is the value placed in the baud rate register brg and the second is the value of the brgh bit with the control register ucr2. the brgh bit decides if the baud rate generator is to be used in a high speed mode or low speed mode, which in turn determines the formula that is used to calculate the baud rate. the value n in the brg register which is used in the following baud rate calculation formula determines the division factor . note that n is the decimal value placed in the brg register and has a range of between 0 and 255. ucr2 brgh bit 0 1 baud rate (br) f sys / [ ?? (n+1)] f sys / [1 ? (n+1)] by programming the brgh bit which allows selection of the related formula and programming the required value in the brg register , the required baud rate can be setup. note that because the actual baud rate is determ ined using a discrete value, n, placed in the brg register , there will be an error associated between the actual and requested value. the following example shows how the brg register value n and the error value can be calculated. rev. 1.10 13 ? de ? e ?? e ? 1 ?? ? 01 ? rev. 1.10 137 de?e??e? 1?? ?01? HT45F75 body fat scale flash mcu HT45F75 body fat scale flash mcu calculating the register and error values for a clock frequency of 4mhz, and with brgh cleared to zero determine the brg register value n, the actual baud rate and the error value for a desired baud rate of 4800. from the above table the desired baud rate br=f sys / [64 (n+1)] re-arranging this equation gives n=[f sys / (br64)] - 1 giving a value for n=[4000000 / (480064)] - 1=12.0208 to obtain the closest value, a decim al value of 12 should be placed into the brg register . this gives an actual or calculated baud rate value of br=4000000 / [64(12 + 1)]=4808 therefore the error is equal to (4808 - 4800) / 4800=0.16% the following tables show actual values of baud rate and error values for the two values of brgh. baud rate k/bps baud rates for brgh=0 f sys =4mhz f sys =3.579545mhz f sys =7.159mhz brg kbaud error (%) brg kbaud error (%) brg kbaud error (%) 0.3 ? 07 0.300 0.1 ? 185 0.300 0.00 1. ? 51 1. ? 0 ? 0.1 ? ?? 1.190 -0.83 9 ? 1. ? 03 0. ? 3 ? . ? ? 5 ? . ? 0 ? 0.1 ? ?? ? . ? 3 ? 1.3 ? ?? ? .380 -0.83 ? .8 1 ? ? .808 0.1 ? 11 ? . ?? 1 - ? .90 ?? ? .8 ? 3 1.3 ? 9. ? ? 8.9 ? 9 - ? .99 5 9.3 ? 1 - ? .90 11 9.33 ? - ? .90 19. ? ? ? 0.833 8.51 ? 18. ?? 3 - ? .90 5 18. ?? 3 - ? .90 38. ? ? 3 ? . ? 8 ? - ? .90 57. ? 0 ?? .500 8.51 0 55.930 - ? .90 1 55.930 - ? .90 115. ? 0 111.859 - ? .90 baud rates and error values for brgh=0 baud rate k/bps baud rates for brgh=1 f sys =4mhz f sys =3.579545mhz f sys =7.159mhz brg kbaud error (%) brg kbaud error (%) brg kbaud error (%) 0.3 1. ? ? 07 1. ? 0 ? 0.1 ? 185 1. ? 03 0. ? 3 ? . ? 103 ? . ? 0 ? 0.1 ? 9 ? ? . ? 0 ? 0. ? 3 185 ? . ? 0 ? 0. ? 3 ? .8 51 ? .808 0.1 ? ?? ? .7 ? -0.83 9 ? ? .811 0. ? 3 9. ? ? 5 9. ? 15 0.1 ? ?? 9.7 ? 7 1.3 ? ?? 9.5 ? 0 -0.83 19. ? 1 ? 19. ? 31 0.1 ? 11 18. ?? 3 - ? .90 ?? 19. ? 5 ? 1.3 ? 38. ? ? 35.71 ? - ? .99 5 37. ? 8 ? - ? .90 11 37. ? 8 ? - ? .90 57. ? 3 ?? .5 8.51 3 55.930 - ? .90 7 55.930 - ? .90 115. ? 1 1 ? 5 8.51 1 111.8 ? - ? .90 3 111.8 ? - ? .90 ? 50 0 ? 50 0 baud rates and error values for brgh=1 rev. 1.10 13? de?e??e? 1?? ?01? rev. 1.10 137 de ? e ?? e ? 1 ?? ? 01 ? HT45F75 body fat scale flash mcu HT45F75 body fat scale flash mcu uart setup and control for data transfer , the uar t functio n utilizes a non-return-to-zero, more commonly known as nrz, format. this is composed of one start bit, eight or nine data bits, and one or two stop bits. parity is supported by the uar t hardware, and can be setup to be even, odd or no parity . for the most common data format, 8 data bits along with no parity and one stop bit, denoted as 8, n, 1, is used as the default setti ng, which is the setting at power -on. the number of data bits and stop bits, along with t he pa rity, a re se tup by pr ogramming t he c orresponding b no, pr t, pr en, a nd st ops b its in the ucr1 register . the baud rate used to transmit and receive data is setup using the internal 8-bit baud rate generator , while the data is transmitted and received lsb frst. although the uar t transmitter and receiver are functionally independent, they both use the same data format and baud rate. in all cases stop bits will be used for data transmission. enabling/disabling the uart the basic on/of f function of the internal uar t function is controlled using the uar ten bit in the ucr1 register . if the uar ten, txen and rxen bits are set, then these two uar t pins will act as n ormal t x o utput p in a nd r x i nput p in r espectively. i f n o d ata i s b eing t ransmitted o n t he t x pin, then it will default to a logic high value. clearing the uar ten bit will disable the tx and rx pins and allow these two pins to be used as normal i/o or other pin-shared functional pins. when the uar t functi on is disabled the buf fer will be reset to an empty condition, at the same time discarding any remai ning residual data. disabling the uar t will also reset the error and status fags with bits txen, rxen, txbrk, rxif , oerr, ferr, perr and nf being cleared while bits tidle, txif and ridle will be set. the remaining control bits in the ucr1, ucr2 and brg registers will remain unaf fected. if the uar ten bit in the ucr1 register is cleared while the uart is active, then all pending transmissions and receptions will be immediate ly suspended and the uar t will be reset to a condition as defned above. if the uart is then subsequently re-enabled, it will restart again in the same confguration. data, parity and stop bit selection the format of the dat a to be transferred, is com posed of various fact ors such as dat a bi t length, parity on/of f, parity type, address bits and the number of stop bits. these factors are determined by the setup of various bits within the ucr1 register . the bno bit controls the number of data bits which can be set to either 8 or 9, the pr t bit controls the choice of odd or even parity , the pren bit controls the parity on/of f function and the st ops bit decides whether one or two stop bits are to be used. the following table shows various formats for data transmission. the address bit identifes the frame as an address character . the number of stop bits, which can be either one or two, is independent of the data length. start bit data bits address bits parity bits stop bit example of 8-bit data formats 1 8 0 0 1 1 7 0 1 1 1 7 1 0 1 example of 9-bit data formats 1 9 0 0 1 1 8 0 1 1 1 8 1 0 1 transmitter receiver data format the following diagram shows the trans mit and receive waveforms for both 8-bit and 9-bit data formats. rev. 1.10 138 de ? e ?? e ? 1 ?? ? 01 ? rev. 1.10 139 de?e??e? 1?? ?01? HT45F75 body fat scale flash mcu HT45F75 body fat scale flash mcu uart transmitter data word lengths of either 8 or 9 bits, can be selected by programmi ng the bno bit in the ucr1 register. when bno bit is set, the word length will be set to 9 bits. in this case the 9th bit, which is the msb, needs to be stored in the tx8 bit in the ucr1 register . at the transmitter core lies the transmitter shift register , more commonly known as the tsr, whos e data is obtained from the transmit d ata r egister, wh ich i s k nown a s t he t xr r egister. t he d ata t o b e t ransmitted i s l oaded into this txr register by the applic ation program. the tsr register is not written to with new data until the stop bit from the previous transmission has been sent out. as soon as this stop bit has been transmitted, the tsr can then be loaded with new data from the txr register , if it is available. it should be noted that the tsr register , unlike many other registers, is not directly mapped into the data memory area and as such is not available to the application program for direct read/write operations. an actual transmission of data will normally be enabled when the txen bit is set, but the data will not be transmitted until the txr register has been loaded with data and the baud rate generator ha s de fned a shi ft c lock sourc e. however , t he t ransmission c an a lso be i nitiated by frst loading data into the txr register , after which the txen bit can be set. when a transmission of data begins, the tsr is normally empty , in which case a transfer to the txr register will result in an immed iate transfer to the tsr. if during a transmission the txen bit is cleared, the transmission will i mmediately c ease a nd t he t ransmitter wi ll b e r eset. t he t x output p in wi ll t hen r eturn t o t he i /o or other pin-shared function. transmitting data when the uar t is transmitting data, the data is shifted on the tx pin from the shift register , with the leas t s ignificant bit firs t. in the trans mit mode, the tx r regis ter forms a buf fer betw een the internal bus and the transmitter shift register . it should be noted that if 9-bit data format has been selected, then the msb will be take n from the tx8 bit in the ucr1 register . the steps to initiate a data transfer can be summarized as follows: ? make the correct selection of the bno, pr t, pren and st ops bits to defne the required word length, parity type and number of stop bits. ? setup the brg register to select the desired baud rate. ? set the txen bit to ensure that the tx pin is used as a uart transmitter pin. ? access the usr register and write the data that is to be transmitted into the txr register . note that this step will clear the txif bit. ? this sequence of events can now be repeated to send additional data. it should be noted that when txif=0, data will be inhibited from being written to the txr register . clearing the txif fag is always achieved using the following software sequence: 1. a usr register access 2. a txr register write execution the read-only txif fag is set by the uar t hardware and if set indic ates that the txr register is empty and that other data can now be written into the txr register without overwriting the previous data. if the teie bit is set then the txif fag will generate an interrupt. rev. 1.10 138 de?e??e? 1?? ?01? rev. 1.10 139 de ? e ?? e ? 1 ?? ? 01 ? HT45F75 body fat scale flash mcu HT45F75 body fat scale flash mcu during a data transmission, a write instruction to the txr register will place the data into the txr register, which will be copied to the shift register at the end of the present transmission. when there is no data transmission in progress, a write instruction to the txr register will place the data directly into the shift register , resulting in the commencement of data transmission, and the txif bit being immediately se t. w hen a fra me t ransmission i s c omplete, whi ch ha ppens a fter st op bi ts a re se nt or after the break frame, the tidle bit will be set. t o clear the tidle bit the following software sequence is used: 1. a usr register access 2. a txr register write execution note that both the txif and tidle bits are cleared by the same software sequence. transmit break if the txbrk bit is set then break characters will be sent on the next transmission. break character transmission consists of a start bit, followed by 13n 0 bits and stop bits, where n=1, 2, etc. if a break character is to be transmitted then the txbrk bit must be frst set by the application program, then c leared t o gene rate t he st op bit s. t ransmitting a brea k cha racter wi ll not gene rate a t ransmit interrupt. note that a break condition length is at least 13 bits long. if the txbrk bit is continually kept at a logic high level then the transmitter circuitry will transmit continuous break characters. after the application program has cleared the txbrk bit, the transmitter will fnish transmitting the last break character and subsequently send out one or two stop bits. the automatic logic highs at the end of the last break character will ensure that the start bit of the next frame is recognized. uart receiver the uar t is capable of receiving word lengths of either 8 or 9 bits. if the bno bit is set, the word length will be set to 9 bits with the msb being stored in the rx8 bit of the ucr1 register . at the receiver core lies the receive serial shift register , commonly known as the rsr. the data which is receive d on the rx external input pin, is sent to the data recovery block. the data recovery block operating speed is 16 times that of the baud rate, while the main receiv e serial shifter operates at the baud rate. after the rx pin is sampled for the stop bit, the received data in rsr is transferred to the receive data register, if the register is empty. the data which is received on the external rx input pin is sample d three times by a majority detect circuit to determine the logic level that has been placed onto the rx pin. it should be noted that the rsr register , unlike many other registers, is not directly mapped into the data memory area and as such is not available to the application program for direct read/write operations. receiving data when the uar t receiver is receiv ing data, the data is serially shifted in on the external rx input pin, lsb frst. in the read mode, the rxr register forms a buf fer between the internal bus and the receiver shift register . the rxr register is a two byte deep fifo data buf fer, where two bytes can be held in the fifo while a third byte can continue to be received. note that the application program must e nsure t hat t he d ata i s r ead f rom r xr b efore t he t hird b yte h as b een c ompletely sh ifted in, o therwise t his t hird b yte wi ll b e d iscarded a nd a n o verrun e rror oe rr wi ll b e su bsequently indicated. the steps to initiate a data transfer can be summarized as follows: ? make the correct selection of bno, pr t, pren and st ops bits to defne the word length, parity type and number of stop bits. ? setup the brg register to select the desired baud rate. ? set the rxen bit to ensure that the rx pin is used as a uart receiver pin. at this point the receiver will be enabled which will begin to look for a start bit. rev. 1.10 1 ? 0 de ? e ?? e ? 1 ?? ? 01 ? rev. 1.10 1?1 de?e??e? 1?? ?01? HT45F75 body fat scale flash mcu HT45F75 body fat scale flash mcu when a character is received the following sequence of events will occur: ? the rxif bit in the usr register will be set when rxr register has data available, at least one more character can be read. ? when the contents of the shift register have been transferred to the rxr register , then if the rie bit is set, an interrupt will be generated. ? if during reception, a frame error , noise error , parity error , or an overrun error has been detected, then the error fags can be set. the rxif bit can be cleared using the following software sequence: 1. a usr register access 2. an rxr register read execution receive break any break character received by the uar t will be managed as a framing error . the receiver will count and expect a certain number of bit times as specifed by the value s programmed into the bno and st ops bits. if the break is much longer than 13 bit times, the reception will be considered as complete a fter t he num ber of bi t t imes spe cifed by bno a nd st ops. t he rxif bi t i s se t, fe rr is set, zeros are loaded into the rece ive data register , interrupts are generated if appropriate and the ridle bit is set. if a long break signal has been detected and the receiver has received a start bit, the data bits and the invalid stop bit, which sets the ferr fag, the receiver must wait for a valid stop bit before looking for the next start bit. the receiver will not make the ass umption that the break condition on the line is the next start bit. a break is regarded as a character that contains only zeros with the ferr fag set. the break character will be loaded into the buf fer and no further data will be received until stop bits are received. it should be noted that the ridle read only fag will go high when the stop bits have not yet been received. the reception of a break character on the uar t registers will result in the following: ? the framing error fag, ferr, will be set. ? the receive data register, rxr, will be cleared. ? the oerr, nf, perr, ridle or rxif fags will possibly be set. idle status when the receiver is reading data, which means it will be in between the detection of a start bit and the readin g of a stop bit, the receiver status fag in the usr register , otherwise known as the ridle fag, will have a zero value. in between the reception of a stop bit and the detection of the next start bit, the ridle fag will have a high value, which indicates the receiver is in an idle condition. receiver interrupt the read only receive interrupt fag rxif in the usr register is set by an edge generated by the receiver. an i nterrupt i s ge nerated i f rie =1, whe n a word i s t ransferred from t he re ceive shi ft register, rsr, to the receive data register , rxr. an overrun error can also generate an interrupt if rie=1. rev. 1.10 1?0 de?e??e? 1?? ?01? rev. 1.10 1 ? 1 de ? e ?? e ? 1 ?? ? 01 ? HT45F75 body fat scale flash mcu HT45F75 body fat scale flash mcu managing receiver errors several types of reception errors can occur within the uart module, the following section describes the various types and how they are managed by the uart. overrun error C oerr flag the rxr register is composed of a two byte deep fifo data buf fer, where two bytes can be held in the fifo register , while a third byte can continue to be received. before this third byte has been entirely shifted in, the data should be read from the rxr register . if this is not done, the overrun error fag oerr will be consequently indicated. in the event of an overrun error occurring, the following will happen: ? the oerr fag in the usr register will be set. ? the rxr contents will not be lost. ? the shift register will be overwritten. ? an interrupt will be generated if the rie bit is set. the o err flag can be cleared by an acces s to the u sr regis ter follow ed by a read to the rx r register. noise error C nf flag over-sampling i s u sed f or d ata r ecovery t o i dentify v alid i ncoming d ata a nd n oise. i f n oise i s detected within a frame the following will occur: ? the read only noise fag, nf, in the usr register will be set on the rising edge of the rxif bit. ? data will be transferred from the shift register to the rxr register. ? no interrupt will be generated. however this bit rises at the same time as the rxif bit which itself generates an interrupt. note t hat t he nf fa g i s r eset b y a usr r egister r ead o peration f ollowed b y a n r xr r egister r ead operation. framing error C ferr flag the read only framing error fag, ferr, in the usr register , is set if a zero is detected instead of stop bits. if two stop bits are selecte d, both stop bits must be high, otherwise the ferr fag will be set. the ferr fag is buffered along with the received data and is cleared on any reset. parity error C perr flag the read only parity error fag, perr, in the usr register , is set if the parity of the received word is incorrect. this error fag is only applicable if the parity is enabled, pren=1, and if the parity type, odd or even is selected. the read only perr fag is buf fered along with the received data bytes. it is cleared on any reset. it should be noted that the ferr and perr fags are buf fered along with the corresponding word and should be read before reading the data word. rev. 1.10 1 ?? de ? e ?? e ? 1 ?? ? 01 ? rev. 1.10 1?3 de?e??e? 1?? ?01? HT45F75 body fat scale flash mcu HT45F75 body fat scale flash mcu uart module interrupt structure several i ndividual uar t c onditions c an ge nerate a uar t i nterrupt. w hen t hese c onditions e xist, a low pulse will be generated to get the attention of the microcontroller . these conditions are a transmitter data register empty , trans mitter idle, receiver data available, receiver overrun, addres s detect and an rx pin wake-up. when any of these conditions are created, if the global interrupt enable bit, multi-f unction interrupt enable bit and its corresponding interrupt control bit are enabled and the s tack is not full, the program w ill jump to its corresponding interrupt vector w here it can be serviced before returning to the main program. four of these conditions have the corresponding usr register fags which will generate a uar t interrupt if its associate d interrupt enable control bit in the ucr2 register is set. the two transmitter interrupt conditions have their own corresponding enable c ontrol bi ts, whi le t he t wo re ceiver i nterrupt c onditions ha ve a sha red e nable c ontrol bi t. these enable bits can be used to mask out individual uart interrupt sources. the address det ect condit ion, whi ch i s al so a uar t i nterrupt source, does not have an associa ted flag, but will generate a uar t interrupt when an address detect condition occurs if its function is e nabled by se tting t he adde n bi t i n t he ucr2 re gister. an rx pi n wa ke-up, whi ch i s a lso a uart interrupt source, does not have an associated fag, but will generate a uar t interrupt if the microcontroller i s woke n up from idl e0 or sl eep m ode by a fa lling e dge on t he rx pi n, i f t he wake and rie bits in the ucr2 register are set. note that in the event of an rx wake-up interrupt occurring, there will be a certain period of delay , commonly known as the system start-up t ime, for the oscillator to restart and stabilize before the system resumes normal operation. note t hat t he usr r egister f lags a re r ead o nly a nd c annot b e c leared o r se t b y t he a pplication program, neither will they be cleared when the program jumps to the corresponding interrupt servicing routine, as is the cas e for some of the other interrupts. the flags will be cleared automatically whe n c ertain a ctions a re t aken by t he uar t, t he de tails of whi ch a re gi ven i n t he uart regi ster se ction. the overal l uar t i nterrupt ca n be disable d or ena bled by t he rel ated interrupt enable control bits in the interrupt control registers of the microcontroller to decide whether the interrupt requested by the uart module is masked out or allowed. t?ans?itte? e?pty flag txif usr registe? t?ans?itte? idle flag tidle re?eive? ove??un flag oerr re?eive? data availa?le rxif adden rx pin wake-up wake 0 1 0 1 0 1 rx7 if bno=0 rx8 if bno=1 ucr? registe? or rie 0 1 tiie 0 1 teie 0 1 uart inte??upt request flag uif ucr? registe? uie mfi1 registe? mf1e intc1 registe? emi intc0 registe? uart interrupt scheme rev. 1.10 1?? de?e??e? 1?? ?01? rev. 1.10 1 ? 3 de ? e ?? e ? 1 ?? ? 01 ? HT45F75 body fat scale flash mcu HT45F75 body fat scale flash mcu address detect mode setting the address detect mode bit, adden, in the ucr2 register , enables this special mode. if this bit is enabled then an additional qualifer will be placed on the generation of a receiver data available interrup t, which is requested by the rxif fag. if the adden bit is enabled, then when data is available, an interrupt will only be generated, if the highest received bit has a high value. note t hat t he mfne , uie a nd e mi i nterrupt e nable bi ts m ust a lso be e nabled for c orrect i nterrupt generation. this highes t addres s bit is the 9th bit if bn o=1 or the 8th bit if bn o=0. if this bit is high, then the received word will be defined as an address rather than data. a data a vailable interrupt will be generated every time the last bit of the received word is set. if the adden bit is not enabled, then a receiver data a vailable interrupt will be generated each time the rx if flag i s se t, i rrespective o f t he d ata l ast b it st atus. t he a ddress d etect m ode a nd p arity e nable a re mutually exclusive functions. therefore if the address detect mode is enabled, then to ensure correct operation, the parity function should be disabled by resetting the parity enable bit to zero. adden bit 9 if bno=1, bit 8 if bno=0 uart interrupt generated 0 0 1 1 0 1 adden bit function uart module power down and wake-up when the mcu system clock is switched of f, the uar t will cease to function. if the mcu executes the hal t instruction and switches of f the system clock while a transmission is still in progress, then the transmission will be paused until the uar t clock source derived from the microcontroller is activated. in a similar way , if the mcu executes the hal t instruction and switches of f the system clock w hile receiving data, then the reception of data w ill likewise be paus ed. when the mcu enters the idle or sleep mode, note that the usr, ucr1, ucr2, transmit and receive registers, as well as the brg register will not be af fected. it is recomm ended to make sure frst that the uar t data transmission or reception has been finished before the microcontroller enters the idle or sleep mode. the ua rt function contains a receiver rx pin wake-up function, which is enabled or disabled by the w ake bit in the ucr2 register . if this bit, along with the uar t enable bit, uar ten, the receiver enable bit, rxen and the receiver interrupt bit, rie, are all set before the mcu enters the idle0 or sleep mode, then a fall ing edge on the rx pin will wake up the mcu from the idle0 or sl eep mo de. no te t hat a s i t t akes c ertain sy stem c lock c ycles a fter a wa ke-up, b efore n ormal microcontroller operation resumes, any data received during this time on the rx pin will be ignored. for a uar t wake-up interrupt to occur , in addition to the bits for the wake-up being set, the global interrupt enable bit, emi, and the uar t interrupt enable bit, uie, must also be set. if these two bits are not set then only a wake up event will occur and no interrupt will be generated. note also that as it takes certain system clock cycles after a wake-up before normal microcontroller resumes, the uart interrupt will not be generated until after this time has elapsed. rev. 1.10 1 ?? de ? e ?? e ? 1 ?? ? 01 ? rev. 1.10 1?5 de?e??e? 1?? ?01? HT45F75 body fat scale flash mcu HT45F75 body fat scale flash mcu ir modulation interface the uar t i nterface ha s a n i ntegrated ir m odulation i nterface. in frared m odulation fr equency control by register irctrl0, its value is any integer between 0 and 127. infrared modulation: when txd=0 only, the ir modulation will produce infrared mixing and output data. t o meet the needs of both pnp and npn infrared driver tube, located in the register irctrl0 bit7 irtc, control the polarity of the output of the infrared modulation. irtc=0 for positive polarity output, suitable for pnp transistor driver; ir tc=1 for a negative output, suitable for the npn driver . see below: f?a??y txd ir txd (irtc=0) ir txd (irtc=1) 1 0 0 0 00 11 1 111 0 irctrl0 register bit 7 6 5 4 3 2 1 0 na ? e irtc irdc ? irdc5 irdc ? irdc3 irdc ? irdc1 irdc0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7 irtc : ir modulation output polarity select 0: negative 1: positive bit 6~0 irdc6~irdc0 : ir modulation frequency divider coeffcient fcarry=(f / (irdc+1))/2 irctrl1 register bit 7 6 5 4 3 2 1 0 na ? e irme0 r/w r/w por 0 bit 7~1 unimplemented, read as 0 bit 0 irme0 : uart tx ir modulation control 0: uart tx ir modulation disable 1: uart tx ir modulation enable rev. 1.10 1?? de?e??e? 1?? ?01? rev. 1.10 1 ? 5 de ? e ?? e ? 1 ?? ? 01 ? HT45F75 body fat scale flash mcu HT45F75 body fat scale flash mcu interrupts interrupts are an important part of any microcontroller s ystem. when an external event or an internal function such as a t imer module or an a/d converter requires microcontroller attention, their corresponding interrupt will enforce a temporary suspension of the main program allowing the microcontroller to direct attention to their respective needs. the device contains several external interrupt and internal interrupts functions. the external interrupts are generated by the action of the external int0~int1 pins, while the internal interrupts are generated by various internal functions such as the tms, t ime base, lvd, eeprom and the a/d converter. interrupt registers overall interrupt control, w hich bas ically means the s etting of reques t flags w hen certain microcontroller conditions occur and the setting of interrupt enable bits by the application program, is cont rolled by a se ries of regi sters, l ocated i n t he spe cial purpose dat a me mory. the frst i s t he intc0~intc2 registers which setup the primary interrupts, the second is the mfi0~mfi3 registers which setup the multi-function interrupts. finally there is an integ register to setup the external interrupt trigger edge type. each regist er contai ns a number of enable bit s to enable or disa ble indivi dual regist ers as wel l as interrupt flags to indicate the presence of an interrupt request. the naming convention of these follows a specifc pattern. first is listed an abbreviated interrupt type, then the (optional) number of that interrupt followed by either an e for enable/disable bit or f for request fag. function enable bit request flag notes glo ? al emi intn pin intne intnf n=0~1 multi-fun ? tion mfne mfnf n=0~3 a/d conve ? te ? ade adf ti ? e base tbne tbnf n=0~1 lvd lve lvf eeprom dee def sim sie sif i ? c ti ? e out i ? ctoe i ? ctof uart uie uif tm tnpe tnpf n=0~ ? tnae tnaf interrupt register bit naming conventions rev. 1.10 1 ?? de ? e ?? e ? 1 ?? ? 01 ? rev. 1.10 1?7 de?e??e? 1?? ?01? HT45F75 body fat scale flash mcu HT45F75 body fat scale flash mcu register name bit 7 6 5 4 3 2 1 0 integ int1s1 int1s0 int0s1 int0s0 intc0 mf0f int1f int0f mf0e int1e int0e emi intc1 mf1f tb1f tb0f adf mf1e tb1e tb0e ade intc ? mf3f mf ? f mf3e mf ? e mfi0 t0af t0pf t0ae t0pe mfi1 uif sif def lvf uie sie dee lve mfi ? i ? ctof t1af t1pf i ? ctoe t1ae t1pe mfi3 t ? af t ? pf t ? ae t ? pe interrupt register contents integ register bit 7 6 5 4 3 2 1 0 na ? e int1s1 int1s0 int0s1 int0s0 r/w r/w r/w r/w r/w por 0 0 0 0 bit 7~4 unimplemented, read as 0 bit 3~2 int1s1~int1s0 : interrupt edge control for int1 pin 00: disable 01: rising edge 10: falling edge 11: rising and falling edges bit 1~0 int0s1~int0s0 : interrupt edge control for int0 pin 00: disable 01: rising edge 10: falling edge 11: rising and falling edges intc0 register bit 7 6 5 4 3 2 1 0 na ? e mf0f int1f int0f mf0e int1e int0e emi r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 bit 7 unimplemented, read as 0 bit 6 mf0f : multi-function interrupt 0 request fag 0: no request 1: interrupt request bit 5 int1f : int1 interrupt request fag 0: no request 1: interrupt request bit 4 int0f : int0 interrupt request fag 0: no request 1: interrupt request bit 3 mf0e : multi-function interrupt 0 control 0: disable 1: enable bit 2 int1e : int1 interrupt control 0: disable 1: enable rev. 1.10 1?? de?e??e? 1?? ?01? rev. 1.10 1 ? 7 de ? e ?? e ? 1 ?? ? 01 ? HT45F75 body fat scale flash mcu HT45F75 body fat scale flash mcu bit 1 int0e : int0 interrupt control 0: disable 1: enable bit 0 emi : global interrupt control 0: disable 1: enable intc1 register bit 7 6 5 4 3 2 1 0 na ? e mf1f tb1f tb0f adf mf1e tb1e tb0e ade r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7 mf1f : multi-function interrupt 1 request fag 0: no request 1: interrupt request bit 6 tb1f : t ime base 1 interrupt request fag 0: no request 1: interrupt request bit 5 tb0f : t ime base 0 interrupt request fag 0: no request 1: interrupt request bit 4 adf : a/d converter interrupt request fag 0: no request 1: interrupt request bit 3 mf1e : multi-function interrupt 1 control 0: disable 1: enable bit 2 tb1e : t ime base 1 interrupt control 0: disable 1: enable bit 1 tb0e : t ime base 0 interrupt control 0: disable 1: enable bit 0 ade : a/d converter interrupt control 0: disable 1: enable rev. 1.10 1 ? 8 de ? e ?? e ? 1 ?? ? 01 ? rev. 1.10 1?9 de?e??e? 1?? ?01? HT45F75 body fat scale flash mcu HT45F75 body fat scale flash mcu intc2 register bit 7 6 5 4 3 2 1 0 na ? e mf3f mf ? f mf3e mf ? e r/w r/w r/w r/w r/w por 0 0 0 0 bit 7~6 unimplemented, read as 0 bit 5 mf3f : multi-function interrupt 3 request fag 0: no request 1: interrupt request bit 4 mf2f : multi-function interrupt 2 request fag 0: no request 1: interrupt request bit 3~2 unimplemented, read as 0 bit 1 mf3e : multi-function interrupt 3 control 0: disable 1: enable bit 0 mf2e : multi-function interrupt 2 control 0: disable 1: enable mfi0 register bit 7 6 5 4 3 2 1 0 na ? e t0af t0pf t0ae t0pe r/w r/w r/w r/w r/w por 0 0 0 0 bit 7~6 unimplemented, read as 0 bit 5 t0af : tm0 comparator a match interrupt request fag 0: no request 1: interrupt request bit 4 t0pf : tm0 comparator p match interrupt request fag 0: no request 1: interrupt request bit 3~2 unimplemented, read as 0 bit 1 t0ae : tm0 comparator a match interrupt control 0: disable 1: enable bit 0 t0pe : tm0 comparator p match interrupt control 0: disable 1: enable rev. 1.10 1?8 de?e??e? 1?? ?01? rev. 1.10 1 ? 9 de ? e ?? e ? 1 ?? ? 01 ? HT45F75 body fat scale flash mcu HT45F75 body fat scale flash mcu mfi1 register bit 7 6 5 4 3 2 1 0 na ? e uif sif def lvf uie sie dee lve r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7 uif : uart interrupt request fag 0: no request 1: interrupt request bit 6 sif : sim interrupt request fag 0: no request 1: interrupt request bit 5 def : data eeprom interrupt request fag 0: no request 1: interrupt request bit 4 lvf : lvd interrupt request fag 0: no request 1: interrupt request bit 3 uie : uart interrupt control 0: disable 1: enable bit 2 sie : sim interrupt control 0: disable 1: enable bit 1 dee : data eeprom interrupt control 0: disable 1: enable bit 0 lve : lvd interrupt control 0: disable 1: enable rev. 1.10 150 de ? e ?? e ? 1 ?? ? 01 ? rev. 1.10 151 de?e??e? 1?? ?01? HT45F75 body fat scale flash mcu HT45F75 body fat scale flash mcu mfi2 register bit 7 6 5 4 3 2 1 0 na ? e i ? ctof t1af t1pf i ? ctoe t1ae t1pe r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 bit 7 i2ctof : i 2 c t ime out interrupt request fag 0: no request 1: interrupt request bit 6 unimplemented, read as 0 bit 5 t1af : tm1 comparator a match interrupt request fag 0: no request 1: interrupt request bit 4 t1pf : tm1 comparator p match interrupt request fag 0: no request 1: interrupt request bit 3 i2ctoe : i 2 c t ime out interrupt control 0: disable 1: enable bit 2 unimplemented, read as 0 bit 1 t1ae : tm1 comparator a match interrupt control 0: disable 1: enable bit 0 t1pe : tm1 comparator p match interrupt control 0: disable 1: enable mfi3 register bit 7 6 5 4 3 2 1 0 na ? e t ? af t ? pf t ? ae t ? pe r/w r/w r/w r/w r/w por 0 0 0 0 bit 7~6 unimplemented, read as 0 bit 5 t2af : tm2 comparator a match interrupt request fag 0: no request 1: interrupt request bit 4 t2pf : tm2 comparator p match interrupt request fag 0: no request 1: interrupt request bit 3~2 unimplemented, read as 0 bit 1 t2ae : tm2 comparator a match interrupt control 0: disable 1: enable bit 0 t2pe : tm2 comparator p match interrupt control 0: disable 1: enable rev. 1.10 150 de?e??e? 1?? ?01? rev. 1.10 151 de ? e ?? e ? 1 ?? ? 01 ? HT45F75 body fat scale flash mcu HT45F75 body fat scale flash mcu interrupt operation when the conditions for an interrupt event occur , such as a tm comparator p , comparator a match or a/d conversion completion etc., the relevant interrupt request fag will be set. whether the request fag actually generates a program jump to the relevant interrupt vector is determined by the condition of the interrupt enabl e bit. if the enable bit is set high then the program will jump to its relevant vector; if the enable bit is zero then although the interrupt request fag is set an actual interrupt will not be generated and the program will not jump to the relevant interrupt vector . the global interrupt enable bit, if cleared to zero, will disable all interrupts. when an interrupt is generated, the program counter, which stores the address of the next instruction to be executed, will be transferred onto the stack. the program counter will then be loaded with a new address which will be the value of the corresponding interrupt vector . the microcontroller will then fetch its next instruction from this interrupt vector . the instruction at this vector will usually be a jmp which will jump to another section of program which is known as the interrupt service routine. here is located the code to control the appropriate interrupt. the interrupt service routine must be terminated w ith a reti, w hich retrieves the original p rogram counter address from the st ack a nd a llows t he m icrocontroller t o c ontinue wi th n ormal e xecution a t t he p oint wh ere t he interrupt occurred. the various interrupt enable bits, together with their associated request flags, are shown in the accompanying diagrams with their order of priority . some interrupt sources have their own individual vector w hile others s hare the s ame multi-function interrupt vector . o nce an interrupt subroutine is serviced, all the other interrupts will be blocked, as the global interrupt enable bit, emi bit will be cleared automatically . this will prevent any further interrupt nesting from occurring. however, i f ot her i nterrupt re quests oc cur duri ng t his i nterval, a lthough t he i nterrupt wi ll not be immediately serviced, the request fag will still be recorded. if an interrupt requires immediate servicing while the program is alread y in another interrupt service routine, the emi bit should be set after entering the routine, to allow interrupt nesting. if the stack is full, the interrupt request will not be acknowledged, even if the related interrupt is enabled, until the stack pointer is decremented. if immediate service is desired, the stack must be prevented from becoming full. in case of simultaneous requests, the accompanying diagram shows the priority that is a pplied. al l o f t he i nterrupt r equest fa gs wh en se t wi ll wa ke-up t he d evice i f i t i s i n sl eep o r idle mode, however to prevent a wake-up from occurring the corresponding fag should be set before the device is in sleep or idle mode. rev. 1.10 15 ? de ? e ?? e ? 1 ?? ? 01 ? rev. 1.10 153 de?e??e? 1?? ?01? HT45F75 body fat scale flash mcu HT45F75 body fat scale flash mcu 0 ? h 0ch ? 0h 10h vector low p ? io ? it y high request flags ena ? le bits maste ? e na ? le request flags ena ? le bits emi auto disa ? led in isr inte ?? upt n a ? e inte ?? upt n a ? e emi emi emi emi t1af tm1 a t1ae t1pf tm1 p t1pe int 0f int 0 pin int 0e mf0f m. fun ? t . 0 mf0e mf ? f m. fun ? t . ? mf ? e adf a/d ade xxf legend request flag C no auto ? es et in isr xxf request flag C auto ? es et in isr xxe ena ? le bit t0af tm0 a t0pf tm0 p t0ae t0pe 18h emi tb1 f ti ? e b ase 1 tb1 e 08h emi int1f int1 pin int1e ?? h emi t ? af tm ? a t ? ae t ? pf tm ? p t ? pe mf3f m. fun ? t . 3 mf3e 1 ? h tb0 f ti ? e b ase 0 1ch emi def eeprom dee lvf lvd lve mf1f m. fun ? t . 1 mf1e uif uart uie sif sim sie inte ?? upt s ? ont ained within multi - fun ? t ion inte ?? upt s emi tb0 e i ? ctof i ? cto i ? ctoe interrupt structure rev. 1.10 15? de?e??e? 1?? ?01? rev. 1.10 153 de ? e ?? e ? 1 ?? ? 01 ? HT45F75 body fat scale flash mcu HT45F75 body fat scale flash mcu external interrupt the external interrupts are controlled by signal transitions on the pins int0~int1. an external interrupt request will take place when the external interrupt request fags, int0f~int1f , are set, which will occur when a transition, whose type is chosen by the edge select bits, appears on the external interrupt pins. t o allow the program to branch to its respective interrupt vector address, the global interrupt enable bit, emi, and respective external interrupt enable bit, int0e~int1e, must frst be set. additionally the correct interrupt edge type must be selected using the integ register to enable the externa l interrupt functio n and to choose the trigger edge type. as the external interrupt pins are pin-shared with i/o pins, they can only be configured as external interrupt pins if their external interrupt enable bit in the corresponding interrupt register has been set. the pin must also be setup as an input by setting the corresponding bit in the port control register . when the interrupt is enabled, the stack is not full and the correct transition type appears on the external interrupt pin, a subroutine call to the external interrupt vector , will take place. when the interrupt is serviced, the external interrupt request fags, int0f~int1f , will be automatically reset and the emi bit will be automatically cleared to disable other interrupts. note that any pull-high resistor selections on the external interrupt pins will remain valid even if the pin is used as an external interrupt input. the integ re gister i s use d t o se lect t he t ype of a ctive e dge t hat wi ll t rigger t he e xternal i nterrupt. a choice of ei ther risi ng or fall ing or both edge types ca n be chosen to tri gger an ext ernal int errupt. note that the integ register can also be used to disable the external interrupt function. a/d converter interrupt the a/d converter interrupt is controlled by the termination of an a/d conversion process. an a/d converter interrupt request will take place when the a/d converter interrupt request fag, adf , is set, which occurs when the a/d conversion process fnishes. t o allow the program to branch to its respective interrupt vector a ddress, the global interrupt enable bit, emi, a nd a/ d interrupt enable bit, ade, must frst be set. when the interrupt is enabled, the stack is not full and the a/d conversion process has ended, a subroutine call to the a/d converter interrupt vector , will take place. when the interrupt is serviced, the a/d converter interrupt fag, adf , will be automatically cleared. the emi bit will also be automatically cleared to disable other interrupts. multi-function interrupt within t his de vice t here a re up t o f our mul ti-function i nterrupts. unl ike t he ot her i ndependent interrupts, these interrupts have no independent source, but rather are formed from other existing interrupt sources, na mely the t m interrupts, l vd interrupt, uart interrupt, sim interrupt, i 2 c t ime out interrupt and eeprom interrupt. a multi-function interrupt request will take place when any of the multi-function interrupt request flags, mfnf are set. the multi-function interrupt flags will be set when any of their included functions generate an interrupt request fag. t o allow the program to branch to its respective interrupt vector address, when the multi-func tion interrupt is enabled and the stack is not full, and either one of the interrupts contained within each of multi-function interrupt occurs, a subroutine call to one of the multi-function interrupt vectors will take place. when the interrupt is serviced, the related multi- function request fag will be automatically reset and the emi bit will be automatically cleared to disable other interrupts. however, i t m ust be not ed t hat, a lthough t he mul ti-function int errupt fa gs wi ll be a utomatically reset when the interrupt is serviced, the request fags from the original source of the multi-function interrupts, namely the tm interrupts, l vd interrupt, uar t interrupt, sim interrupt, i 2 c time out interrupt and eeprom interrupt will not be automatically reset and must be manually reset by the application program. rev. 1.10 15 ? de ? e ?? e ? 1 ?? ? 01 ? rev. 1.10 155 de?e??e? 1?? ?01? HT45F75 body fat scale flash mcu HT45F75 body fat scale flash mcu serial interface module interrupt the serial interface module interrupt, also known as the sim interrupt, is contained within the multi-function interrupt. an sim interrupt request will take place when the sim interrupt request flag, sif , is set, which occurs when a byte of data has been received or transmitted by the sim interface. t o allow the program to branch to its res pective interrupt vector addres s, the global interrupt enable bit, em i, and the s erial interface interrupt enable bit, s ie, and m uti-function interrupt enable bits, must frst be set. when the interrupt is enabled, the stack is not full and a byte of data has been transmitted or received by the sim interface, a subroutine call to the respective multi-function interrupt vector , will take place. when the serial interface interrupt is serviced, the emi bit wi ll be aut omatically cl eared t o disable othe r i nterrupts, however only t he mul ti-function interrupt reques t f ag w ill be als o automatically cleared. a s the s if f ag w ill not be automatically cleared, it has to be cleared by the application program. time base interrupts the function of the t ime base interrupts is to provide regular time signal in the form of an internal interrupt. they are controlled by the overfow signals from their respective timer functions. when these happens their respective interrupt request flags, tb0f or tb1f will be set. t o allow the program to branch to their respective interrupt vector addresses, the global interrupt enable bit, emi and t ime base enable bits, tb0e or tb1e, must frst be set. when the interrupt is enabled, the stack is not full and the t ime base overfow s, a subroutine call to their res pective vector locations will take place. when the interrupt is serviced, the respective interrupt request fag, tb0f or tb1f , will be automatically reset and the emi bit will be cleared to disable other interrupts. the purpose of the t ime base interrupt is to provide an interrupt signal at fxed time periods. their clock sources originate from the internal clock source f tb . this f tb input clock passes through a divider, the division ratio of which is selected by programming the appropriate bits in the tbc register to obtain longer interrupt periods whose value ranges. the clock source that generates f tb , which in turn controls the t ime base interrupt period, can originate from several dif ferent sources, as shown in the system operating mode section. ? ? ? time base interrupt rev. 1.10 15? de?e??e? 1?? ?01? rev. 1.10 155 de ? e ?? e ? 1 ?? ? 01 ? HT45F75 body fat scale flash mcu HT45F75 body fat scale flash mcu tbc register bit 7 6 5 4 3 2 1 0 na ? e tbon tbck tb11 tb10 lxtlp tb0 ? tb01 tb00 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 1 1 0 1 1 1 bit 7 tbon : tb0 and tb1 control 0: disable 1: enable bit 6 tbck : select f tb clock 0: f 1: f /4 bit 5~4 tb11~tb10 : select t ime base 1 t ime-out period 00: 4096/f tb 01: 8192/f tb 10: 16384/f tb 11: 32768/f tb bit 3 lxtlp : lxt low power control 0: quick start mode 1: low power mode bit 2~0 tb02~tb00 : select t ime base 0 t ime-out period 000: 256/f tb 001: 512/f tb 010: 1024/f tb 011: 2048/f tb 100: 4096/f tb 101: 8192/f tb 110: 16384/f tb 111: 32768/f tb i 2 c time out interrupt the i 2 c t ime out interrupt operates is contained within the multi-function interrupt. an i 2 c t ime out i nterrupt r equest wi ll t ake p lace whe n t he i 2 c t ime ou t i nterrupt r equest f lag, i 2ctof, i s set, which occurs when an i 2 c time-out counter overfows. t o allow the program to branch to its respective interrupt vector address, the global interrupt enable bit, emi, i 2 c time out interrupt enable bit, i2ct oe, and associated multi-function interrupt enable bit, must frst be set. when the interrupt is enabled, the s tack is not full and an i 2 c time-out counter overfow occurs , a s ubroutine call to the respective multi-function interrupt, will take place. when the i 2 c tim e out interrupt is serviced, the emi bit will be automatically cleared to disable other interrupts, however only the multi- function interrupt reques t f ag w ill be als o automatically cleared. a s the i2ct of f ag w ill not be automatically cleared, it has to be cleared by the application program. rev. 1.10 15 ? de ? e ?? e ? 1 ?? ? 01 ? rev. 1.10 157 de?e??e? 1?? ?01? HT45F75 body fat scale flash mcu HT45F75 body fat scale flash mcu uart interrupt the uar t i nterrupt i s c ontained wi thin t he mu lti-function i nterrupt. se veral i ndividual uar t conditions c an g enerate a uar t i nterrupt. w hen t hese c onditions e xist, a l ow p ulse wi ll b e generated to get the attention of the microcontroller . these conditions are a transmitter data register empty, transmitter idle, receiver data available, receiver overrun, address detect and an rx pin wake-up. t o allow the program to branch to the respective interrupt vector addresses, the global interrupt enable bit, emi, multi-function enable bit, mfne and uar t interrupt enable bit, uie, must frst be set. when the interrup t is enabled, the stack is not full and any of these conditions are created, a subroutine call to the respective multi-function interrupt vector , will take place. when the interrupt is service d, the emi bit will be automatically cleared to disable other interrupts, the multi- function interrupt request fag will be also automatically cleared. however , the usr register fags will be cleared automatically when certain actions are taken by the uar t, the details of which are given in the uart section. eeprom interrupt the eeprom interrupt is contained within the multi-function interrupt. an eeprom interrupt request will take place when the eeprom interrupt request flag, def , is set, which occurs when an eeprom w rite cycl e ends. t o allow the program to branch to its respective interrupt vector address, the global interrupt enable bit, emi, and eeprom interrupt enable bit, dee, and associated multi-function interrupt enable bit, must frst be set. when the interrupt is enabled, the stack i s n ot f ull a nd a n e eprom w rite c ycle e nds, a su broutine c all t o t he r espective e eprom interrupt vector will take place. when the eeprom interrupt is serviced, the emi bit will be automatically clea red to disable other interrupts, however only the multi-function interrupt request fag will be also automatically cleared. as the def fag will not be automatically cleared, it has to be cleared by the application program. lvd interrupt the l ow v oltage de tector i nterrupt i s c ontained wi thin t he mu lti-function i nterrupt. an l vd interrupt reques t w ill take place w hen the l vd interrupt request flag, l vf, is s et, w hich occurs when the low v oltage detector function detects a low power supply voltage. t o allow the program to branch to its respective interrupt vector address, the global interrupt enable bit, emi, low v oltage interrupt enable bit, l ve, and associated multi-function interrupt enable bit, must frst be set. when the interrupt is enabled, the stack is not full and a low voltage conditio n occurs, a subroutine call to the multi-function interrupt vector , will take place. when the low v oltage interrupt is serviced, the emi bit wi ll be aut omatically cl eared t o disable othe r i nterrupts, however only t he mul ti-function interrupt request fag will be also automatically cleared. as the l vf fag will not be automatically cleared, it has to be cleared by the application program. tm interrupts the compact and periodic t ype tms have two interrupts. all of the tm interrupts are contained within the multi-function interrupts. for each of the compact and periodic t ype tms there are two interrupt request fags tnpf and tnaf and two enable bits tnpe and tnae. a tm interrupt request will take place when any of the tm request flags are set, a situation which occurs when a tm comparator p or a match situation happens. to allow the program to branch to its respective interrupt vector address, the global interrupt enable bit, emi, respective tm interrupt enable bit, and relevant multi-function interrupt enable bit, mfne, must frst be set. when the interrupt is enabled, the stack is not full and a tm comparator match situation occurs, a subroutine call to the relevant multi-function interrupt vector locations, will take place. when the tm interrupt is serviced, the emi bit will be automatically cleared to disable other interrupts, however only the related mfnf fag will be automatically cleared. as the tm interrupt request fags will not be automatically cleared, they have to be cleared by the application program. rev. 1.10 15? de?e??e? 1?? ?01? rev. 1.10 157 de ? e ?? e ? 1 ?? ? 01 ? HT45F75 body fat scale flash mcu HT45F75 body fat scale flash mcu interrupt wake-up function each of the int errupt funct ions has the capa bility of waki ng up the mi crocontroller when in the sleep or idle mode. a wake-up is generated when an interrupt request fag changes from low to high and is independent of whether the interrupt is enabled or not. therefore, even though the device is in the sleep or idle mode and its system oscillator stopped, situations such as external edge transitions on the external interrupt pins or a low power supply voltag e may cause their respective interrupt fag to be set high and consequently generate an interrupt. care must therefore be taken if spurious wake-up situations are to be avoided. if an interrupt wake-up function is to be disabled then the corresponding interrupt request fag should be set high before the device enters the sleep or idle mode. the interrupt enable bits have no effect on the interrupt wake-up function. programming considerations by di sabling t he re levant i nterrupt e nable bi ts, a re quested i nterrupt c an be pre vented from be ing serviced, however , once an interrupt request flag is set, it will remain in this condition in the interrupt register until the corresponding interrupt is serviced or until the request fag is cleared by the application program. where a certain interrupt is contained w ithin a m ulti-function interrupt, then w hen the interrupt service routine is executed, as only the multi-function interrupt request flags, mfnf , will be automatically cleared, the individual request flag for the function needs to be cleared by the application program. it is recommended that programs do not use the call instruction within the interrupt service subroutine. interrupts often occur in an unpredictable manner or need to be serviced immediately . if only one stack is left and the inte rrupt is not well controlled, the original control sequence will be damaged once a call subroutine is executed in the interrupt subroutine. every i nterrupt h as t he c apability o f wa king u p t he m icrocontroller wh en i t i s i n sl eep o r i dle mode, the wake up being generated when the interrupt request fag changes from low to high. if it is required to prevent a certain interru pt from waking up the microcontrol ler then its respective request fag should be frst set high before enter sleep or idle mode. as only the program counter is pushed onto the stack, then when the interrupt is serviced, if the contents of the accumulator , status register or other registers are altered by the interrupt service program, t heir c ontents shoul d be sa ved t o t he m emory a t t he be ginning of t he i nterrupt se rvice routine. t o return from an interrupt subroutine, either a ret or reti instruction may be executed. the reti instruction in addition to executing a return to the main program also automatically sets the emi bit high to allow further interrupts. the ret instruction however only executes a return to the main program leaving the emi bit in its present zero state and therefore disabling the execution of further interrupts. rev. 1.10 158 de ? e ?? e ? 1 ?? ? 01 ? rev. 1.10 159 de?e??e? 1?? ?01? HT45F75 body fat scale flash mcu HT45F75 body fat scale flash mcu low voltage detector C lvd t he device has a low v oltage detector function, also known as l vd. this enabled the device to monitor the power supply voltage, v dd , or l vdin pin input voltage, and provide a warning signal should i t fa ll be low a c ertain l evel. t his fu nction m ay be e specially use ful i n ba ttery a pplications where the s upply voltage w ill gradually reduce as the battery ages , as it allows an early w arning battery low signal to be generated. the low v oltage detector also has the capability of generating an interrupt signal. lvd register the l ow v oltage de tector func tion i s c ontrolled usi ng a si ngle registe r wi th t he nam e l vdc. three bits in this register , vl vd2~vlvd0, are used to select l vd function operation condition. a low volta ge condition is indicated when the l vdo bit is set. if the l vdo bit is low , this indicates that the v dd or l vdin pin input voltage is above the reference voltage. the l vden bit is used to control the overall on/of f function of the low voltage detector . setting the bit high will enable the low voltage detector . clearing the bit to zero will switch of f the internal low voltage detector circuits. as the low voltage detector will consume a certain amount of power , it may be desirable to switch off the circuit when not in use, an important consideration in power sensitive battery powered applications. lvdc register bit 7 6 5 4 3 2 1 0 na ? e lvdo lvden vlvd ? vlvd1 vlvd0 r/w r r/w r/w r/w r/w por 0 0 0 0 0 bit 7~6 unimplemented, read as 0 bit 5 : lvd output flag 0: no low v oltage detect 1: low v oltage detect bit 4 : low v oltage detector control 0: disable 1: enable bit 3 unimplemented, read as 0 bit 2~0 : lvd function operation condition selection 000: lvdin pin, v lvdin 1.04v 001: 2.2v 010: 2.4v 011: 2.7v 100: 3.0v 101: 3.3v 110: 3.6v 111: 4.0v when t he vl vd b it fe ld i s se t t o 0 00b, t he l vd f unction wi ll b e i mplemented b y comparing the l vd reference voltage with a voltage value of 1.04v which is derived from the lvdin pin. otherwise, the lvd function will operate by comparing the lvd reference voltage with a specifc voltage value which is generated by the internal l vd circuit when the vl vd bit feld is set to any other value except 000b. rev. 1.10 158 de?e??e? 1?? ?01? rev. 1.10 159 de ? e ?? e ? 1 ?? ? 01 ? HT45F75 body fat scale flash mcu HT45F75 body fat scale flash mcu lvd operation the low v oltage detector function operates by comparing the power supply voltage, v dd , or lvdin pin input voltage with a pre-specifed voltage level stored in the l vdc register . when the power supply voltage, v dd , or l vdin pin input voltage falls below this pre-determined value, the lvdo bit will be set high indicating a low voltage condition. the low v oltage detector function is supplied by a reference voltage , which will be automatically enabled. when the device is powered down the low voltage detector will remain active if the l vden bit is high. after enabling the low voltage detector , a time delay t lvds should be allowed for the circuitry to stabilise before reading the lvdo bit. note also that as the v dd or l vdin pin input voltage may rise and fall rather slowly , at the voltage nears that of v lvd , there may be multiple bit lvdo transitions. lvd operation the low v oltage detector also has its own interrupt which is contained within one of the multi- function interrupts, providing an alternative means of low voltage detection, in addition to polling the l vdo bit. the interrupt will only be generated after a delay of t lvd after the l vdo bit has been set high by a low voltage condition. when the device is powered down the low v oltage detector will rema in active if the l vden bit is high. in this case, the l vf interrupt request fag will be set, causing an interrupt to be generated if v dd or l vdin pin input voltag e falls below the preset l vd voltage. this will cause the device to wake-up from the sleep or idle mode, however if the low voltage detector wake up function is not required then the l vf fag should be frst set high before the device enters the sleep or idle mode. when l vd functi on is enabled, it is recommenced to clear l vd fag frst, and then enables interrupt function to avoid mistake action. rev. 1.10 1 ? 0 de ? e ?? e ? 1 ?? ? 01 ? rev. 1.10 1?1 de?e??e? 1?? ?01? HT45F75 body fat scale flash mcu HT45F75 body fat scale flash mcu body fat measurement function the body fat circu it consists of a sine wave generator , an amplifer and a flter . the circuit has been designed for maximum fexibility and has a high degree of functional integration to implement a body fat measurement function. the circuit is powered by the ldo. sine wave generator the sine wave generator consists of a frequency divider , counter , ram, 10-bit dac and op0. the circuit can generate a sine wave output with a frequency range of 5khz ~ 200kh z using a 329 bit ram for the sine wave pattern simulation. the frequency divider will multiply by dn/m to generate a clock for the counter . the following points must be noted to understand how the sine wave is generated: ? system clock/m=sine wave frequency ? system clock (dn/m)=the count rate of the counter ? m must be a multiple of n and 8 ? m=ndn ? dnr=dn/2 ? dn: sine wave cycle data numerical value (dn 64) ? dnr: the data numerical value of the 1/2 sine wave cycle stored in ram (dnr 32) refer to the following table and fgure for more details. system frequency 4.8mhz 9.6mhz 14.4mhz the frequency of sine wave(khz) 200 100 50 5 200 100 50 5 200 100 50 5 m ?? ? 8 9 ? 9 ? 0 ? 8 9 ? 19 ? 19 ? 0 7 ? 1 ?? ? 88 ? 880 n 1 1 ? ? 0 1 ? ? ? 0 3 3 ? ? 0 dn ?? ? 8 ? 8 ? 8 ? 8 ? 8 ? 8 ? 8 ?? ? 8 ? 8 ? 8 dnr 1 ? ?? ?? ?? ?? ?? ?? ?? 1 ? ?? ?? ?? p0 p1 p? -51? 511 0 p dnr-1 p dnr-? p dnr-3 rev. 1.10 1?0 de?e??e? 1?? ?01? rev. 1.10 1 ? 1 de ? e ?? e ? 1 ?? ? 01 ? HT45F75 body fat scale flash mcu HT45F75 body fat scale flash mcu only a half sine wave pattern p0~p dnr-1 is generated which is stored in ram sector 2 with an address range of 80h~bfh. the sine wave pat tern dat a bi ts [7:0] are stored with even addresses while the sine wave pattern data bit [8] is stored with an odd address. once the sine wave generator is enabled , the cpu will not be able to write or read data to/from this ram area. the sine generator will read the ram data and transmit it to the 10-bit dac. the device will read the half sine wave pattern from the ram and generate the actual sine waveform on the sin pin. refer to the following diagram: ?'s co?ple?ent 0 1 + sine[8:0] dac 0 1 d[9:0] d[8:0] d[9] 1 0 dn_cnt>=dnr 80h 81h 8?h 83h bdh bch bbh beh bfh . . . 50 6hfwru sine0[8:0] sine1[8:0] sine?[8:0] sine3[8:0] . . . . . sine30[8:0] sine31[8:0] sine wave pattern sine0[7:0] sine0[8] sine1[7:0] sine1[8] sine30[7:0] sine30[8] sine31[7:0] sine31[8] rev. 1.10 1 ?? de ? e ?? e ? 1 ?? ? 01 ? rev. 1.10 1?3 de?e??e? 1?? ?01? HT45F75 body fat scale flash mcu HT45F75 body fat scale flash mcu sgc register bit 7 6 5 4 3 2 1 0 na ? e sgen bren r/w r/w r/w por 0 0 bit 7 sgen : sine generator enable bit 0: disable 1: enable when this bit is equal to 0, the op0 and 10-bit dac will be in a power down mode. bit 6~5 unimplemented, read as 0 bit 4 bren : bias resistor enable bit 0: disable - power down mode 1: enable - normal mode when this bit is enabled, it will generate a 0.5 av voltage for the non-inverting input of opa1 and op a2. bit 3~0 unimplemented, read as 0 sgn register bit 7 6 5 4 3 2 1 0 na ? e d5 d ? d3 d ? d1 d0 r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 bit 7~6 unimplemented, read as 0 bit 5~0 d5~d0 : sine generator data system frequency multiplicator, n, is equal to d[5:0] + 1. sgdnr register bit 7 6 5 4 3 2 1 0 na ? e d ? d3 d ? d1 d0 r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 bit 7~5 unimplemented, read as 0 bit 4~0 d4~d0 : data number of sample 1/2 si ne wa ve c ycle num erical va lue i s st ored i n ram se ctor 2. dnr i s e qual t o d[4:0] + 1. amplifer the amplifer consists of op1, op2, a 6-bit dac and analog switches. op2 is a differential amplifer with 1~5 multiple gain. the 6-bit dac of fers a reference voltage to the non-inverting input of op2. the user can turn on and of f switch 0 to 7 to obtain a reference resistor voltage and a body resistor voltage. the body and reference impedance can be obtained by using the sw0 ~ sw7 switches. refer to following table for this impedance switching. switch sw0 sw1 sw2 sw3 sw4 sw5 sw6 sw7 foot i ? pedan ? e o o o 5hihuhqfhn o o o 5hihuhqfh o o o o: swit ? h is on rev. 1.10 1?? de?e??e? 1?? ?01? rev. 1.10 1 ? 3 de ? e ?? e ? 1 ?? ? 01 ? HT45F75 body fat scale flash mcu HT45F75 body fat scale flash mcu opac register bit 7 6 5 4 3 2 1 0 na ? e opaen op ? g3 op ? g ? op ? g1 op ? g0 r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 bit 7 opaen : op amplifer control bit 0: disable 1: enable when this bit is equal to"0", op1, op2 and 6-bit dac will be in a power down mode. bit 6~4 unimplemented, read as 0 bit 3~0 op2g3~op2g0 : op2 gain control bit 0001: 1.14 0010: 1.31 0011: 1.5 0100: 1.73 0101: 2 0110: 2.33 0111: 2.75 1000: 3.285 1001: 4 1010: 5 others: 1 swc register bit 7 6 5 4 3 2 1 0 na ? e sw7 sw ? sw5 sw ? sw3 sw ? sw1 sw0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7 sw7 : switch 7 control bit 0: off 1: on bit 6 sw6 : switch 6 control bit 0: off 1: on bit 5 sw5 : switch 5 control bit 0: off 1: on bit 4 sw4 : switch 4 control bit 0: off 1: on bit 3 sw3 : switch 3 control bit 0: off 1: on bit 2 sw2 : switch 2 control bit 0: off 1: on bit 1 sw1 : switch 1 control bit 0: off 1: on bit 0 sw0 : switch 0 control bit 0: off 1: on rev. 1.10 1 ?? de ? e ?? e ? 1 ?? ? 01 ? rev. 1.10 1?5 de?e??e? 1?? ?01? HT45F75 body fat scale flash mcu HT45F75 body fat scale flash mcu daco register bit 7 6 5 4 3 2 1 0 na ? e d5 d ? d3 d ? d1 d0 r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 bit 7~6 unimplemented, read as 0 bit 5~0 d5~d0 : 6-bit dac output voltage output voltage=0.5av ((d[5:0] + 1) / 64) filter the flter consists of cp0, a pmos transistor and some analog switches. the flter contains a peak detection function for which an external capacitor will store the peak value for transmission to the adc. switches sw8 and sw9 are for capacitor discharge purposes. ftrc register bit 7 6 5 4 3 2 1 0 na ? e ftren hysen sw9 sw8 r/w r/w r/w r/w r/w por 0 0 0 0 bit 7 ftren : filter control bit 0: disable 1: enable when this bit is equal to "0", cp0 and pmos enter power down mode. bit 6~5 unimplemented, read as 0 bit 4 hysen : reserved bit bit 3~2 unimplemented, read as "0" bit 1 sw9 : switch 9 control bit 0: off 1: on bit 0 sw8 : switch 8 control bit 0: off 1: on rev. 1.10 1?? de?e??e? 1?? ?01? rev. 1.10 1 ? 5 de ? e ?? e ? 1 ?? ? 01 ? HT45F75 body fat scale flash mcu HT45F75 body fat scale flash mcu confguration options confguration options refer to certa in options within the mcu that are programmed into the device during the programming process. during the development process, these options are selected using the ht -ide software development tools. as these options are programmed into the device using the hardwa re programm ing tools, once they are sel ected they cannot be changed la ter using the application program. all options must be defned for proper system function, the details of which are shown in the table. no. options oscillator options 1 high speed syste ? os ? illato ? sele ? tion f h : 1. hxt ? . hirc ? hirc f ? equen ? y sele ? tion: 1. ? .8mhz ? . 9. ? mhz 3. 1 ? . ? mhz 3 low speed syste ? os ? illato ? sele ? tion f sub : 1. lxt ? . lirc watchdog timer options ? wdt fun ? tion: 1. always ena ? le d ? . cont ? olled ? y wdt cont ? ol registe ? 5 wdt clo ? k sele ? tion f s : 1. f sub ? . f sys / ? application circuits to cp0n rfc vdd pb3/xt1 pb?/xt? vss 10? 51k 33k 10? 10uf vdd avdd 100k 10? vcm an0 an1 vrefp vrefn avdd an? an3 avss 105 avdd 10? 10? HT45F75 1k 1k 1k 1k sin fvl fil rf1 fvr fir rf? 10? ?.7k 1k ?00 33k 33k rev. 1.10 1 ?? de ? e ?? e ? 1 ?? ? 01 ? rev. 1.10 1?7 de?e??e? 1?? ?01? HT45F75 body fat scale flash mcu HT45F75 body fat scale flash mcu instruction set introduction central to the successful operation of any microcontroller is its instruction set, which is a set of program instruction codes that direc ts the microcontroller to perform certain operations. in the case of holtek microcontroller , a comprehensive and fexible set of over 60 instructions is provided to enable programmers to implement their application with the minimum of programming overheads. for easier understanding of the various instruction codes, they have been subdivided into several functional groupings. instruction timing most instructions are implemented within one instruction cycle. the exceptions to this are branch, call, or table read instructions where two ins truction cycles are required. one instruction cycle is equal to 4 system clock cycles, therefore in the case of an 8mhz system oscillator , most instructions would be i mplemented wi thin 0.5 s a nd bra nch or c all i nstructions woul d be i mplemented wi thin 1s. although instructions which require one more cycle to implement are generally limited to the jmp , call, ret , reti and table read instructions, it is important to realize that any other instructions which involve manipulation of the program counter low register or pcl will also take one more cycle to implement. as instructions which change the contents of the pcl will imply a direct j ump t o t hat ne w a ddress, one m ore c ycle wi ll be re quired. e xamples of suc h i nstructions would be "clr pcl" or "mov pcl, a". for the case of skip instructions, it must be noted that if the result of the comparison involves a skip operation then this will also take one more cycle, if no skip is involved then only one cycle is required. moving and transferring data the t ransfer of da ta wi thin t he m icrocontroller progra m i s one of t he m ost fre quently use d operations. making use of three kinds of mov instructions, data can be transferred from registers to the accumulator and vice-versa as well as being able to move specifc immediate data directly into the ac cumulator. one of t he m ost i mportant da ta t ransfer a pplications i s t o re ceive da ta from t he input ports and transfer data to the output ports. arithmetic operations the ability to perform certain arithm etic operations and data manipula tion is a necessary feature of most m icrocontroller a pplications. w ithin t he hol tek m icrocontroller i nstruction se t a re a ra nge of add and subtract instruction mnemonics to enable the necessary arithmetic to be carried out. care must be taken to ens ure correct handling of carry and borrow data w hen res ults exceed 255 for addition and less than 0 for subtraction. the increment and decrement instructions inc, inca, dec and deca provide a simple means of increasing or decreasing by a value of one of the values in the destination specifed. rev. 1.10 1?? de?e??e? 1?? ?01? rev. 1.10 1 ? 7 de ? e ?? e ? 1 ?? ? 01 ? HT45F75 body fat scale flash mcu HT45F75 body fat scale flash mcu logical and rotate operation the standard logical operations such as and, or, xor and cpl all have their own instruction within t he hol tek m icrocontroller i nstruction se t. as wi th t he c ase of m ost i nstructions i nvolving data m anipulation, d ata m ust p ass t hrough t he ac cumulator wh ich m ay i nvolve a dditional programming steps. in all logical data operations, the zero flag may be set if the result of the operation is zero. another form of logical data manipulation comes from the rotate instructions such as rr, rl, rrc and rlc which provide a simple means of rotating one bit right or left. dif ferent rotate instructions exist depending on program requirements. rotate instructions are useful for serial port progra mming a pplications whe re da ta c an be rot ated from a n i nternal re gister i nto t he ca rry bit from where it can be examined and the necessary serial bit set high or low . another application which rotate data operations are used is to implement multiplication and division calculations. branches and control transfer program branching takes the form of either jumps to specifed locations using the jmp instruction or t o a su broutine usi ng t he cal l i nstruction. t hey di ffer i n t he se nse t hat i n t he c ase of a subroutine call, the program mus t return to the ins truction immediately w hen the s ubroutine has been carried out. this is done by placing a return ins truction " ret" in the s ubroutine w hich w ill cause the program to jump back to the address right after the call instruction. in the case of a jmp instruction, the program simply jumps to the desired location. there is no requirement to jump back to the original jumping of f point as in the case of the call instruction. one special and extremely useful set of branch instructions are the conditional branches. here a decision is frst made regarding the c ondition of a c ertain da ta m emory or i ndividual bi ts. de pending upon t he c onditions, t he program will continue with the next instruction or skip over it and jump to the following instruction. these i nstructions a re t he ke y t o de cision m aking a nd bra nching wi thin t he progra m pe rhaps determined by the condition of certain input switches or by the condition of internal data bits. bit operations the abili ty to provide single bit operations on data memory is an extremely fexible feature of all holtek microcontrollers . this feature is especially useful for output port bit programming where individual bits or port pins can be directly set high or low using either the "set [m].i" or "clr [m]. i" instructions respectively . the feature removes the need for programmers to frst read the 8-bit output port, manipulate the input data to ensure that other bits are not changed and then output the port with the correct new data. this read-modify-write process is take n care of automatically when these bit operation instructions are used. table read operations data st orage i s norm ally i mplemented by usi ng re gisters. however , whe n worki ng wi th l arge amounts of fxed data, the volume involved often makes it inconvenient to store the fxed data in the data memory . t o overcome this problem, holtek microcontrollers allow an area of program memory to be set as a table where data can be directly stored. a set of easy to use instructions provides the means by w hich this fixed data can be referenced and retrieved from the program memory. other operations in addition to the above functional instructions, a range of other instructions also exist such as the "hal t" i nstruction f or po wer-down o perations a nd i nstructions t o c ontrol t he o peration o f the w atchdog t imer for reliable program operations under extreme electric or electromagnetic environments. for their relevant operations, refer to the functional related sections. rev. 1.10 1 ? 8 de ? e ?? e ? 1 ?? ? 01 ? rev. 1.10 1?9 de?e??e? 1?? ?01? HT45F75 body fat scale flash mcu HT45F75 body fat scale flash mcu instruction set summary the i nstructions re lated t o t he da ta m emory a ccess i n t he fol lowing t able c an be used whe n t he desired data memory is located in data memory sector 0. table conventions x: bits immediate data m: data memory address a: accumulator i: 0~7 number of bits addr: program memory address mnemonic description cycles flag affected arithmetic add a ? [ ? ] add data me ? o ? y to acc 1 z ? c ? ac ? ov ? sc addm a ? [ ? ] add acc to data me ? o ? y 1 note z ? c ? ac ? ov ? sc add a ? x add i ?? ediate data to acc 1 z ? c ? ac ? ov ? sc adc a ? [ ? ] add data me ? o ? y to acc with ca ?? y 1 z ? c ? ac ? ov ? sc adcm a ? [ ? ] add acc to data ? e ? o ? y with ca ?? y 1 note z ? c ? ac ? ov ? sc sub a ? x su ? t ? a ? t i ?? ediate data f ? o ? the acc 1 z ? c ? ac ? ov ? sc ? cz sub a ? [ ? ] su ? t ? a ? t data me ? o ? y f ? o ? acc 1 z ? c ? ac ? ov ? sc ? cz subm a ? [ ? ] su ? t ? a ? t data me ? o ? y f ? o ? acc with ? esult in data me ? o ? y 1 note z ? c ? ac ? ov ? sc ? cz sbc a ? x su ? t ? a ? t i ?? ediate data f ? o ? acc with ca ?? y 1 z ? c ? ac ? ov ? sc ? cz sbc a ? [ ? ] su ? t ? a ? t data me ? o ? y f ? o ? acc with ca ?? y 1 z ? c ? ac ? ov ? sc ? cz sbcm a ? [ ? ] su ? t ? a ? t data me ? o ? y f ? o ? acc with ca ?? y ? ? esult in data me ? o ? y 1 note z ? c ? ac ? ov ? sc ? cz daa [ ? ] de ? i ? al adjust acc fo ? addition with ? esult in data me ? o ? y 1 note c logic operation and a ? [ ? ] logi ? al and data me ? o ? y to acc 1 z or a ? [ ? ] logi ? al or data me ? o ? y to acc 1 z xor a ? [ ? ] logi ? al xor data me ? o ? y to acc 1 z andm a ? [ ? ] logi ? al and acc to data me ? o ? y 1 note z orm a ? [ ? ] logi ? al or acc to data me ? o ? y 1 note z xorm a ? [ ? ] logi ? al xor acc to data me ? o ? y 1 note z and a ? x logi ? al and i ?? ediate data to acc 1 z or a ? x logi ? al or i ?? ediate data to acc 1 z xor a ? x logi ? al xor i ?? ediate data to acc 1 z cpl [ ? ] co ? ple ? ent data me ? o ? y 1 note z cpla [ ? ] co ? ple ? ent data me ? o ? y with ? esult in acc 1 z increment & decrement inca [ ? ] in ?? e ? ent data me ? o ? y with ? esult in acc 1 z inc [ ? ] in ?? e ? ent data me ? o ? y 1 note z deca [ ? ] de ?? e ? ent data me ? o ? y with ? esult in acc 1 z dec [ ? ] de ?? e ? ent data me ? o ? y 1 note z rotate rra [ ? ] rotate data me ? o ? y ? ight with ? esult in acc 1 none rr [ ? ] rotate data me ? o ? y ? ight 1 note none rrca [ ? ] rotate data me ? o ? y ? ight th ? ough ca ?? y with ? esult in acc 1 c rrc [ ? ] rotate data me ? o ? y ? ight th ? ough ca ?? y 1 note c rla [ ? ] rotate data me ? o ? y left with ? esult in acc 1 none rl [ ? ] rotate data me ? o ? y left 1 note none rlca [ ? ] rotate data me ? o ? y left th ? ough ca ?? y with ? esult in acc 1 c rlc [ ? ] rotate data me ? o ? y left th ? ough ca ?? y 1 note c rev. 1.10 1?8 de?e??e? 1?? ?01? rev. 1.10 1 ? 9 de ? e ?? e ? 1 ?? ? 01 ? HT45F75 body fat scale flash mcu HT45F75 body fat scale flash mcu mnemonic description cycles flag affected data move mov a ? [ ? ] move data me ? o ? y to acc 1 none mov [ ? ] ? a move acc to data me ? o ? y 1 note none mov a ? x move i ?? ediate data to acc 1 none bit operation clr [ ? ].i clea ? ? it of data me ? o ? y 1 note none set [ ? ].i set ? it of data me ? o ? y 1 note none branch operation jmp add ? ju ? p un ? onditionally ? none sz [ ? ] skip if data me ? o ? y is ze ? o 1 note none sza [ ? ] skip if data me ? o ? y is ze ? o with data ? ove ? ent to acc 1 note none sz [ ? ].i skip if ? it i of data me ? o ? y is ze ? o 1 note none snz [ ? ] skip if data me ? o ? y is not ze ? o 1 note none snz [ ? ].i skip if ? it i of data me ? o ? y is not ze ? o 1 note none siz [ ? ] skip if in ?? e ? ent data me ? o ? y is ze ? o 1 note none sdz [ ? ] skip if de ?? e ? ent data me ? o ? y is ze ? o 1 note none siza [ ? ] skip if in ?? e ? ent data me ? o ? y is ze ? o with ? esult in acc 1 note none sdza [ ? ] skip if de ?? e ? ent data me ? o ? y is ze ? o with ? esult in acc 1 note none call add ? su ?? outine ? all ? none ret retu ? n f ? o ? su ?? outine ? none ret a ? x retu ? n f ? o ? su ?? outine and load i ?? ediate data to acc ? none reti retu ? n f ? o ? inte ?? upt ? none table read operation tabrd [ ? ] read table (specifc page) to tblh and data memory ? note none tabrdl [ ? ] read ta ? le (last page) to tblh and data me ? o ? y ? note none itabrd [ ? ] increment table pointer tblp frst and read table to tblh and data memory ? note none itabrdl [ ? ] increment table pointer tblp frst and read table (last page) to tblh and data me ? o ? y ? note none miscellaneous nop no ope ? ation 1 none clr [ ? ] clea ? data me ? o ? y 1 note none set [ ? ] set data me ? o ? y 1 note none clr wdt clea ? wat ? hdog ti ? e ? 1 to ? pdf swap [ ? ] swap ni ?? les of data me ? o ? y 1 note none swapa [ ? ] swap ni ?? les of data me ? o ? y with ? esult in acc 1 none halt ente ? powe ? down ? ode 1 to ? pdf note: 1. for skip instructions, if the result of the comparison involves a skip then up to three cycles are required, if no skip takes place only one cycle is required. 2. any instruction which changes the contents of the pcl will also require 2 cycles for execution. 3. for the clr wdt instruction the t o and pdf fags may be af fected by the execution status. the t o and pdf fags are cleared after the clr wdt instructions is executed. otherwise the t o and pdf fags remain unchanged. rev. 1.10 170 de ? e ?? e ? 1 ?? ? 01 ? rev. 1.10 171 de?e??e? 1?? ?01? HT45F75 body fat scale flash mcu HT45F75 body fat scale flash mcu extended instruction set the extended instructions are used to support the full range address access for the data memory . when the accessed data memory is located in any data memory sections except sector 0, the extended instructi on can be used to access the data memory instead of using the indirect addressing access to improve the cpu frmware performance. mnemonic description cycles flag affected arithmetic ladd a ? [ ? ] add data me ? o ? y to acc ? z ? c ? ac ? ov ? sc laddm a ? [ ? ] add acc to data me ? o ? y ? note z ? c ? ac ? ov ? sc ladc a ? [ ? ] add data me ? o ? y to acc with ca ?? y ? z ? c ? ac ? ov ? sc ladcm a ? [ ? ] add acc to data ? e ? o ? y with ca ?? y ? note z ? c ? ac ? ov ? sc lsub a ? [ ? ] su ? t ? a ? t data me ? o ? y f ? o ? acc ? z ? c ? ac ? ov ? sc ? cz lsubm a ? [ ? ] su ? t ? a ? t data me ? o ? y f ? o ? acc with ? esult in data me ? o ? y ? note z ? c ? ac ? ov ? sc ? cz lsbc a ? [ ? ] su ? t ? a ? t data me ? o ? y f ? o ? acc with ca ?? y ? z ? c ? ac ? ov ? sc ? cz lsbcm a ? [ ? ] su ? t ? a ? t data me ? o ? y f ? o ? acc with ca ?? y ? ? esult in data me ? o ? y ? note z ? c ? ac ? ov ? sc ? cz ldaa [ ? ] de ? i ? al adjust acc fo ? addition with ? esult in data me ? o ? y ? note c logic operation land a ? [ ? ] logi ? al and data me ? o ? y to acc ? z lor a ? [ ? ] logi ? al or data me ? o ? y to acc ? z lxor a ? [ ? ] logi ? al xor data me ? o ? y to acc ? z landm a ? [ ? ] logi ? al and acc to data me ? o ? y ? note z lorm a ? [ ? ] logi ? al or acc to data me ? o ? y ? note z lxorm a ? [ ? ] logi ? al xor acc to data me ? o ? y ? note z lcpl [ ? ] co ? ple ? ent data me ? o ? y ? note z lcpla [ ? ] co ? ple ? ent data me ? o ? y with ? esult in acc ? z increment & decrement linca [ ? ] in ?? e ? ent data me ? o ? y with ? esult in acc ? z linc [ ? ] in ?? e ? ent data me ? o ? y ? note z ldeca [ ? ] de ?? e ? ent data me ? o ? y with ? esult in acc ? z ldec [ ? ] de ?? e ? ent data me ? o ? y ? note z rotate lrra [ ? ] rotate data me ? o ? y ? ight with ? esult in acc ? none lrr [ ? ] rotate data me ? o ? y ? ight ? note none lrrca [ ? ] rotate data me ? o ? y ? ight th ? ough ca ?? y with ? esult in acc ? c lrrc [ ? ] rotate data me ? o ? y ? ight th ? ough ca ?? y ? note c lrla [ ? ] rotate data me ? o ? y left with ? esult in acc ? none lrl [ ? ] rotate data me ? o ? y left ? note none lrlca [ ? ] rotate data me ? o ? y left th ? ough ca ?? y with ? esult in acc ? c lrlc [ ? ] rotate data me ? o ? y left th ? ough ca ?? y ? note c data move lmov a ? [ ? ] move data me ? o ? y to acc ? none lmov [ ? ] ? a move acc to data me ? o ? y ? note none bit operation lclr [ ? ].i clea ? ? it of data me ? o ? y ? note none lset [ ? ].i set ? it of data me ? o ? y ? note none rev. 1.10 170 de?e??e? 1?? ?01? rev. 1.10 171 de ? e ?? e ? 1 ?? ? 01 ? HT45F75 body fat scale flash mcu HT45F75 body fat scale flash mcu mnemonic description cycles flag affected branch lsz [ ? ] skip if data me ? o ? y is ze ? o ? note none lsza [ ? ] skip if data me ? o ? y is ze ? o with data ? ove ? ent to acc ? note none lsnz [ ? ] skip if data me ? o ? y is not ze ? o ? note none lsz [ ? ].i skip if ? it i of data me ? o ? y is ze ? o ? note none lsnz [ ? ].i skip if ? it i of data me ? o ? y is not ze ? o ? note none lsiz [ ? ] skip if in ?? e ? ent data me ? o ? y is ze ? o ? note none lsdz [ ? ] skip if de ?? e ? ent data me ? o ? y is ze ? o ? note none lsiza [ ? ] skip if in ?? e ? ent data me ? o ? y is ze ? o with ? esult in acc ? note none lsdza [ ? ] skip if de ?? e ? ent data me ? o ? y is ze ? o with ? esult in acc ? note none table read ltabrd [ ? ] read ta ? le to tblh and data me ? o ? y 3 note none ltabrdl [ ? ] read ta ? le (last page) to tblh and data me ? o ? y 3 note none litabrd [ ? ] increment table pointer tblp frst and read table to tblh and data memory 3 note none litabrdl [ ? ] increment table pointer tblp frst and read table (last page) to tblh and data me ? o ? y 3 note none miscellaneous lclr [ ? ] clea ? data me ? o ? y ? note none lset [ ? ] set data me ? o ? y ? note none lswap [ ? ] swap ni ?? les of data me ? o ? y ? note none lswapa [ ? ] swap ni ?? les of data me ? o ? y with ? esult in acc ? none note: 1. for these extended skip instructions, if the result of the comparison involves a skip then up to four cycles are required, if no skip takes place two cycles is required. 2. any extended instruction which changes the contents of the pcl register will also require three cycles for execution. rev. 1.10 17 ? de ? e ?? e ? 1 ?? ? 01 ? rev. 1.10 173 de?e??e? 1?? ?01? HT45F75 body fat scale flash mcu HT45F75 body fat scale flash mcu instruction defnition adc a,[m] add d ata m emory to a cc w ith carry description the c ontents o f t he s pecifed d ata m emory, a ccumulator a nd t he c arry f ag a re a dded. the re sult is s tored in t he a ccumulator. operation acc a cc + [ m] + c affected f ag(s) ov, z , a c, c , s c adcm a,[m] add a cc to d ata m emory w ith carry description the c ontents o f t he s pecifed d ata m emory, a ccumulator a nd t he c arry f ag a re a dded. the re sult is s tored in t he sp ecifed d ata m emory. operation [m] a cc + [ m] + c affected f ag(s) ov, z , a c, c , s c add a,[m] add d ata m emory t o a cc description the c ontents o f t he s pecifed d ata m emory a nd t he a ccumulator a re a dded. the re sult is s tored in t he a ccumulator. operation acc a cc + [ m] affected f ag(s) ov, z , a c, c , s c add a,x add im mediate data to a cc description the c ontents o f t he a ccumulator a nd t he s pecifed im mediate data a re a dded. the re sult is s tored in t he a ccumulator. operation acc a cc + x affected f ag(s) ov, z , a c, c , s c addm a,[m] add a cc to d ata m emory description the c ontents o f t he s pecifed d ata m emory a nd t he a ccumulator a re a dded. the re sult is s tored in t he sp ecifed d ata m emory. operation [m] a cc + [ m] affected f ag(s) ov, z , a c, c , s c and a,[m] logical a nd d ata m emory t o a cc description data i n t he a ccumulator a nd t he s pecifed d ata m emory p erform a b itwise l ogical a nd operation. t he re sult is s tored in t he a ccumulator. operation acc a cc a nd [ m] affected f ag(s) z and a,x logical a nd im mediate data to a cc description data i n t he a ccumulator a nd t he s pecifed im mediate data p erform a b it w ise l ogical a nd operation. t he re sult is s tored in t he a ccumulator. operation acc a cc a nd x affected f ag(s) z andm a,[m] logical a nd a cc to d ata m emory description data i n t he s pecifed d ata m emory a nd t he a ccumulator p erform a b itwise l ogical a nd operation. t he re sult is s tored in t he d ata m emory. operation [m] a cc and [ m] affected f ag(s) z rev. 1.10 17? de?e??e? 1?? ?01? rev. 1.10 173 de ? e ?? e ? 1 ?? ? 01 ? HT45F75 body fat scale flash mcu HT45F75 body fat scale flash mcu call addr subroutine c all description unconditionally c alls a s ubroutine a t t he s pecifed a ddress. th e p rogram c ounter t hen increments b y 1 to o btain t he a ddress o f t he n ext i nstruction w hich i s t hen p ushed o nto t he stack. t he sp ecifed a ddress is t hen loaded a nd t he p rogram c ontinues e xecution f rom t his new a ddress. a s t his instruction re quires a n a dditional op eration, it is a t wo c ycle instruction. operation stack p rogram counter + 1 program c ounter a ddr affected f ag(s) none clr [m] clear d ata m emory description each b it o f t he s pecifed d ata m emory i s cl eared t o 0 . operation [m] 00h affected f ag(s) none clr [m].i clear bi t o f d ata m emory description bit i o f t he s pecifed d ata m emory i s cl eared t o 0 . operation [m].i 0 affected f ag(s) none clr wdt clear w atchdog t imer description the t o, p df f ags a nd t he w dt a re al l c leared. operation wdt cl eared to 0 pdf 0 affected f ag(s) to, p df cpl [m] complement d ata m emory description each b it of t he s pecifed d ata m emory i s l ogically complemented ( 1s complement). b its w hich previously c ontained a 1 a re c hanged to 0 a nd v ice v ersa. operation [m] [m] affected f ag(s) z cpla [m] complement d ata m emory w ith r esult i n a cc description each b it of t he s pecifed d ata m emory i s l ogically complemented ( 1s complement). b its w hich previously c ontained a 1 a re c hanged to 0 a nd v ice v ersa. th e c omplemented r esult i s s tored i n the a ccumulator a nd t he c ontents o f t he d ata m emory r emain u nchanged. operation acc [ m] affected f ag(s) z daa [m] decimal-adjust a cc f or addition w ith r esult i n d ata m emory description convert t he c ontents o f t he a ccumulator v alue to a b cd ( binary c oded d ecimal) v alue resulting f rom t he p revious a ddition o f t wo b cd v ariables. i f t he low n ibble is greater t han 9 or i f a c f ag i s s et, t hen a v alue o f 6 w ill b e a dded to t he l ow n ibble. o therwise t he l ow n ibble remains u nchanged. i f t he h igh n ibble i s g reater t han 9 o r i f t he c f ag i s s et, t hen a v alue o f 6 will b e a dded to t he h igh n ibble. e ssentially, t he decimal c onversion i s p erformed b y a dding 00h, 0 6h, 6 0h o r 6 6h depending o n t he a ccumulator a nd f ag c onditions. o nly t he c f ag may b e a ffected b y t his instruction w hich indicates t hat if t he o riginal b cd s um is greater t han 100, it al lows m ultiple p recision decimal a ddition. operation [m] a cc + 00h or [m] a cc + 06 h o r [m] a cc + 60h o r [m] a cc + 66h affected f ag(s) c rev. 1.10 17 ? de ? e ?? e ? 1 ?? ? 01 ? rev. 1.10 175 de?e??e? 1?? ?01? HT45F75 body fat scale flash mcu HT45F75 body fat scale flash mcu dec [m] decrement d ata m emory description data i n t he s pecifed d ata m emory i s d ecremented b y 1 . operation [m] [ m] ? 1 affected f ag(s) z deca [m] decrement d ata m emory wi th r esult i n a cc description data in t he sp ecifed d ata m emory is d ecremented b y 1 . t he re sult is s tored in t he accumulator. th e c ontents o f t he d ata m emory r emain u nchanged. operation acc [ m] ? 1 affected f ag(s) z halt enter p ower down m ode description this i nstruction s tops t he p rogram e xecution a nd t urns o ff t he s ystem c lock. th e c ontents o f the d ata m emory a nd r egisters a re r etained. th e w dt a nd p rescaler a re c leared. th e p ower down f ag p df i s s et a nd t he w dt t ime-out f ag t o i s c leared. operation to 0 pdf 1 affected f ag(s) to, p df inc [m] increment d ata m emory description data in t he sp ecifed d ata m emory is incremented b y 1 . operation [m] [ m] + 1 affected f ag(s) z inca [m] increment d ata m emory wi th r esult i n a cc description data i n t he sp ecifed d ata m emory i s i ncremented b y 1 . th e re sult i s s tored i n t he a ccumulator. the c ontents o f t he d ata m emory r emain u nchanged. operation acc [ m] + 1 affected f ag(s) z jmp addr jump u nconditionally description the c ontents o f t he p rogram c ounter a re re placed w ith t he sp ecifed a ddress. p rogram execution t hen c ontinues f rom t his n ew a ddress. a s t his re quires t he insertion o f a d ummy instruction w hile t he n ew a ddress is loaded, it is a t wo c ycle instruction. operation program counter addr affected f ag(s) none mov a,[m] move d ata m emory t o a cc description the c ontents o f t he s pecifed d ata m emory a re c opied to t he a ccumulator. operation acc [ m] affected f ag(s) none mov a,x move im mediate data to a cc description the im mediate data s pecifed i s l oaded i nto t he a ccumulator. operation acc x affected f ag(s) none mov [m],a move a cc to d ata m emory description the c ontents o f t he a ccumulator a re c opied to t he s pecifed d ata m emory. operation [m] a cc affected f ag(s) none rev. 1.10 17? de?e??e? 1?? ?01? rev. 1.10 175 de ? e ?? e ? 1 ?? ? 01 ? HT45F75 body fat scale flash mcu HT45F75 body fat scale flash mcu nop no o peration description no o peration i s p erformed. e xecution c ontinues w ith t he n ext i nstruction. operation no operation affected f ag(s) none or a,[m] logical o r d ata m emory to a cc description data i n t he a ccumulator a nd t he s pecifed d ata m emory p erform a b itwise logical o r op eration. t he re sult is s tored in t he a ccumulator. operation acc a cc or [ m] affected f ag(s) z or a,x logical or im mediate data to a cc description data i n t he a ccumulator a nd t he s pecifed im mediate data p erform a b itwise l ogical o r operation. t he re sult is s tored in t he a ccumulator. operation acc a cc or x affected f ag(s) z orm a,[m] logical or a cc to d ata m emory description data i n t he s pecifed d ata m emory a nd t he a ccumulator p erform a b itwise l ogical o r operation. t he re sult is s tored in t he d ata m emory. operation [m] a cc or [ m] affected f ag(s) z ret return from s ubroutine description the p rogram c ounter is re stored f rom t he s tack. p rogram e xecution c ontinues a t t he re stored a ddress. operation program counter s tack affected f ag(s) none ret a,x return f rom su broutine and l oad im mediate data to a cc description the p rogram c ounter i s r estored f rom t he s tack a nd t he a ccumulator l oaded w ith t he s pecifed immediate data. p rogram e xecution c ontinues a t t he r estored a ddress. operation program counter s tack acc x affected f ag(s) none reti return from i nterrupt description the p rogram c ounter is re stored f rom t he s tack a nd t he interrupts a re re -enabled b y s etting t he emi b it. e mi i s t he m aster i nterrupt g lobal e nable b it. i f a n i nterrupt w as p ending w hen t he reti instruction is e xecuted, t he p ending in terrupt ro utine w ill b e p rocessed b efore re turning to t he m ain p rogram. operation program counter s tack emi 1 affected f ag(s) none rl [m] rotate d ata m emory l eft description the c ontents o f t he s pecifed d ata m emory a re r otated l eft b y 1 b it w ith b it 7 r otated i nto b it 0 . operation [m].(i+1) [ m].i; (i=0~6) [m].0 [ m].7 affected f ag(s) none rev. 1.10 17 ? de ? e ?? e ? 1 ?? ? 01 ? rev. 1.10 177 de?e??e? 1?? ?01? HT45F75 body fat scale flash mcu HT45F75 body fat scale flash mcu rla [m] rotate d ata m emory left w ith re sult in a cc description the c ontents o f t he s pecifed d ata m emory a re r otated l eft b y 1 b it w ith b it 7 r otated i nto b it 0 . the r otated r esult i s s tored i n t he a ccumulator a nd t he c ontents o f t he d ata m emory r emain u nchanged. operation acc.(i+1) [ m].i; (i=0~6) acc.0 [ m].7 affected f ag(s) none rlc [m] rotate d ata m emory l eft t hrough carry description the c ontents o f t he s pecifed d ata m emory a nd t he c arry f ag a re r otated l eft b y 1 b it. b it 7 replaces t he c arry b it a nd t he o riginal c arry f ag i s r otated i nto b it 0 . operation [m].(i+1) [ m].i; (i=0~6) [m].0 c c [ m].7 affected f ag(s) c rlca [m] rotate d ata m emory left t hrough c arry w ith re sult in a cc description data i n t he s pecifed d ata m emory and t he carry f ag are r otated l eft b y 1 b it. b it 7 r eplaces t he carry b it a nd t he o riginal c arry f ag i s r otated i nto t he b it 0 . th e r otated r esult i s s tored i n t he accumulator a nd t he c ontents o f t he d ata m emory r emain u nchanged. operation acc.(i+1) [ m].i; (i=0~6) acc.0 c c [ m].7 affected f ag(s) c rr [m] rotate d ata m emory r ight description the contents of t he s pecifed d ata m emory are r otated r ight b y 1 b it w ith b it 0 r otated i nto b it 7 . operation [m].i [ m].(i+1); (i=0~6) [m].7 [ m].0 affected f ag(s) none rra [m] rotate d ata m emory right with result i n a cc description data i n t he s pecifed d ata m emory a nd t he c arry f ag a re r otated r ight b y 1 b it w ith b it 0 rotated i nto b it 7 . th e r otated r esult i s s tored i n t he a ccumulator a nd t he c ontents o f t he data m emory r emain u nchanged. operation acc.i [ m].(i+1); (i=0~6) acc.7 [ m].0 affected f ag(s) none rrc [m] rotate d ata m emory r ight t hrough carry description the c ontents o f t he s pecifed d ata m emory a nd t he c arry f ag a re r otated r ight b y 1 b it. b it 0 replaces t he c arry b it a nd t he o riginal c arry f ag i s r otated i nto b it 7 . operation [m].i [ m].(i+1); (i=0~6) [m].7 c c [ m].0 affected f ag(s) c rev. 1.10 17? de?e??e? 1?? ?01? rev. 1.10 177 de ? e ?? e ? 1 ?? ? 01 ? HT45F75 body fat scale flash mcu HT45F75 body fat scale flash mcu rrca [m] rotate d ata m emory right th rough c arry with result i n a cc description data i n t he s pecifed d ata m emory a nd t he c arry f ag a re r otated r ight b y 1 b it. b it 0 r eplaces the c arry b it a nd t he o riginal c arry f ag i s r otated i nto b it 7 . th e r otated r esult i s s tored i n t he accumulator a nd t he c ontents o f t he d ata m emory r emain u nchanged. operation acc.i [ m].(i+1); (i=0~6) acc.7 c c [ m].0 affected f ag(s) c sbc a,[m] subtract d ata m emory from a cc wi th c arry description the c ontents o f t he s pecifed d ata m emory a nd t he c omplement o f t he c arry f ag a re subtracted f rom t he a ccumulator. t he re sult is s tored in t he a ccumulator. n ote t hat if t he result o f s ubtraction is n egative, t he c f ag w ill b e c leared t o 0 , o therwise if t he re sult is positive o r z ero, t he c f ag w ill b e s et to 1 . operation acc a cc ? [ m] ? c affected f ag(s) ov, z , a c, c , s c, c z sbc a, x subtract im mediate data f rom a cc w ith carry description the immediate da ta a nd t he c omplement o f t he c arry f ag a re s ubtracted f rom t he accumulator. t he re sult is s tored in t he a ccumulator. n ote t hat if t he re sult o f s ubtraction is negative, t he c f ag w ill b e c leared t o 0 , o therwise if t he re sult is p ositive o r z ero, t he c f ag will be se t t o 1 . operation acc a cc - [ m] - c affected f ag(s) ov, z , ac , c , s c, cz sbcm a,[m] subtract d ata m emory from a cc wi th c arry a nd r esult i n d ata m emory description the c ontents o f t he s pecifed d ata m emory a nd t he c omplement o f t he c arry f ag a re subtracted f rom t he a ccumulator. t he re sult is s tored in t he d ata m emory. n ote t hat if t he result o f s ubtraction is n egative, t he c f ag w ill b e c leared t o 0 , o therwise if t he re sult is positive o r z ero, t he c f ag w ill b e s et to 1 . operation [m] a cc ? [ m] ? c affected f ag(s) ov, z , a c, c , s c, c z sdz [m] skip i f decrement d ata m emory i s 0 description the c ontents o f t he s pecifed d ata m emory a re fr st decremented b y 1 . i f t he r esult i s 0 t he following instruction is s kipped. a s t his re quires t he insertion o f a d ummy instruction w hile the n ext instruction is f etched, it is a t wo c ycle instruction. i f t he re sult is n ot 0 t he p rogram proceeds w ith t he f ollowing i nstruction. operation [m] [ m] ? 1 skip if [ m]=0 affected f ag(s) none sdza [m] skip i f decrement d ata m emory i s z ero w ith r esult i n a cc description the c ontents o f t he s pecifed d ata m emory a re fr st decremented b y 1 . i f t he r esult i s 0 , t he following instruction is s kipped. t he re sult is s tored in t he a ccumulator b ut t he sp ecifed data m emory c ontents r emain u nchanged. a s t his r equires t he i nsertion o f a dummy instruction w hile t he n ext instruction is f etched, it is a t wo c ycle instruction. i f t he r esult is n ot 0 , the p rogram p roceeds w ith t he f ollowing instruction. operation acc [ m] ? 1 skip if a cc=0 affected f ag(s) none rev. 1.10 178 de ? e ?? e ? 1 ?? ? 01 ? rev. 1.10 179 de?e??e? 1?? ?01? HT45F75 body fat scale flash mcu HT45F75 body fat scale flash mcu set [m] set d ata m emory description each b it o f t he s pecifed d ata m emory i s s et t o 1 . operation [m] f fh affected f ag(s) none set [m].i set b it o f d ata m emory description bit i o f t he s pecifed d ata m emory i s s et t o 1 . operation [m].i 1 affected f ag(s) none siz [m] skip i f i ncrement d ata m emory i s 0 description the c ontents o f t he sp ecifed d ata m emory a re f rst incremented b y 1 . i f t he re sult is 0 , t he following instruction is s kipped. a s t his re quires t he insertion o f a d ummy instruction w hile the n ext instruction is f etched, it is a t wo c ycle instruction. i f t he re sult is n ot 0 t he p rogram proceeds w ith t he f ollowing i nstruction. operation [m] [ m] + 1 skip if [ m]=0 affected f ag(s) none siza [m] skip if increment d ata m emory is z ero w ith re sult in a cc description the c ontents o f t he sp ecifed d ata m emory a re f rst incremented b y 1 . i f t he re sult is 0 , t he following instruction is s kipped. t he re sult is s tored in t he a ccumulator b ut t he sp ecifed data m emory c ontents r emain u nchanged. a s t his r equires t he i nsertion o f a dummy instruction w hile t he n ext instruction is f etched, it is a t wo c ycle instruction. i f t he re sult is n ot 0 t he p rogram p roceeds w ith t he f ollowing instruction. operation acc [ m] + 1 skip if a cc=0 affected f ag(s) none snz [m].i skip i f d ata m emory i s no t 0 description if t he sp ecifed d ata m emory is n ot 0 , t he f ollowing instruction is s kipped. a s t his re quires t he insertion o f a d ummy instruction w hile t he n ext instruction is f etched, it is a t wo c ycle instruction. i f t he re sult is 0 t he p rogram p roceeds w ith t he f ollowing instruction. operation skip i f [ m].i 0 affected f ag(s) none snz [m] skip i f d ata m emory i s no t 0 description if t he sp ecifed d ata m emory is n ot 0 , t he f ollowing instruction is s kipped. a s t his re quires t he insertion o f a d ummy instruction w hile t he n ext instruction is f etched, it is a t wo c ycle instruction. i f t he re sult is 0 t he p rogram p roceeds w ith t he f ollowing instruction. operation skip i f [ m] 0 affected f ag(s) none sub a,[m] subtract d ata m emory from a cc description the s pecifed d ata m emory i s s ubtracted f rom t he c ontents o f t he a ccumulator. th e r esult i s stored in t he a ccumulator. n ote t hat if t he re sult o f s ubtraction is n egative, t he c f ag w ill b e cleared to 0 , o therwise i f t he r esult i s p ositive o r z ero, t he c f ag w ill b e s et to 1 . operation acc a cc ? [ m] affected f ag(s) ov, z , a c, c , s c, c z rev. 1.10 178 de?e??e? 1?? ?01? rev. 1.10 179 de ? e ?? e ? 1 ?? ? 01 ? HT45F75 body fat scale flash mcu HT45F75 body fat scale flash mcu subm a,[m] subtract d ata m emory from a cc wi th r esult i n d ata m emory description the s pecifed d ata m emory i s s ubtracted f rom t he c ontents o f t he a ccumulator. th e r esult i s stored in t he d ata m emory. n ote t hat if t he re sult o f s ubtraction is n egative, t he c f ag w ill b e cleared to 0 , o therwise i f t he r esult i s p ositive o r z ero, t he c f ag w ill b e s et to 1 . operation [m] a cc ? [ m] affected f ag(s) ov, z , a c, c , s c, c z sub a,x subtract im mediate data f rom a cc description the im mediate data s pecifed b y t he c ode i s s ubtracted f rom t he c ontents o f t he a ccumulator. the re sult is s tored in t he a ccumulator. n ote t hat if t he re sult o f s ubtraction is n egative, t he c fag w ill b e c leared to 0 , o therwise i f t he r esult i s p ositive o r z ero, t he c f ag w ill b e s et to 1 . operation acc a cc ? x affected f ag(s) ov, z , a c, c , s c, c z swap [m] swap ni bbles of d ata m emory description the l ow-order a nd h igh-order n ibbles o f t he s pecifed d ata m emory a re i nterchanged. operation [m].3~[m].0 ? [ m].7~[m].4 affected f ag(s) none swapa [m] swap ni bbles of d ata m emory w ith r esult i n a cc description the l ow-order a nd h igh-order n ibbles o f t he s pecifed d ata m emory a re i nterchanged. th e result i s s tored i n t he a ccumulator. th e c ontents o f t he d ata m emory r emain u nchanged. operation acc.3~acc.0 [ m].7~[m].4 acc.7~acc.4 [ m].3~[m].0 affected f ag(s) none sz [m] skip i f d ata m emory i s 0 description if t he contents of t he s pecifed d ata m emory i s 0, t he following i nstruction i s s kipped. a s t his requires t he insertion o f a d ummy instruction w hile t he n ext instruction is f etched, it is a t wo cycle instruction. i f t he re sult is n ot 0 t he p rogram p roceeds w ith t he f ollowing instruction. operation skip if [ m]=0 affected f ag(s) none sza [m] skip i f d ata m emory i s 0 w ith data m ovement to a cc description the c ontents o f t he s pecifed d ata m emory a re c opied to t he a ccumulator. i f t he v alue i s z ero, the f ollowing instruction is s kipped. a s t his re quires t he insertion o f a d ummy instruction while t he n ext instruction is f etched, it is a t wo c ycle instruction. i f t he re sult is n ot 0 t he program p roceeds w ith t he f ollowing instruction. operation acc [ m] skip if [ m]=0 affected f ag(s) none sz [m].i skip i f b it i of d ata m emory i s 0 description if b it i o f t he sp ecifed d ata m emory is 0 , t he f ollowing instruction is s kipped. a s t his re quires the insertion o f a d ummy instruction w hile t he n ext instruction is f etched, it is a t wo c ycle instruction. i f t he re sult is n ot 0 , t he p rogram p roceeds w ith t he f ollowing instruction. operation skip if [ m].i=0 affected f ag(s) none rev. 1.10 180 de ? e ?? e ? 1 ?? ? 01 ? rev. 1.10 181 de?e??e? 1?? ?01? HT45F75 body fat scale flash mcu HT45F75 body fat scale flash mcu tabrd [m] read ta ble ( specifc p age) to t blh a nd d ata m emory description the low b yte o f t he p rogram c ode ( specifc p age) a ddressed b y t he t able p ointer p air (tblp a nd t bhp) i s mo ved t o t he s pecifed d ata m emory a nd t he h igh by te mo ved t o t blh. operation [m] pr ogram c ode (low by te) tblh pr ogram c ode (high by te) affected f ag(s) none tabrdl [m] read t able (last p age) t o t blh a nd d ata m emory description the l ow by te o f t he pr ogram c ode (last p age) a ddressed by t he t able p ointer (tblp) i s mo ved to t he s pecifed d ata m emory a nd t he h igh b yte m oved to t blh. operation [m] pr ogram c ode (low by te) tblh pr ogram c ode (high by te) affected f ag(s) none itabrd [m] increment ta ble p ointer l ow b yte fr st and r ead ta ble to t blh and d ata m emory description increment ta ble p ointer l ow b yte, t blp, fr st and t hen t he p rogram code addressed b y t he table p ointer ( tbhp and t blp) i s m oved to t he s pecifed d ata m emory and t he hi gh b yte moved t o t blh. operation [m] pr ogram c ode (low by te) tblh pr ogram c ode (high by te) affected f ag(s) none itabrdl [m] increment t able p ointer l ow by te f rst a nd r ead t able (last p age) t o t blh a nd d ata m emory description increment ta ble p ointer l ow b yte, t blp, fr st and t hen t he l ow b yte of t he p rogram code (last p age) addressed b y t he ta ble p ointer ( tblp) i s m oved to t he s pecifed d ata m emory and the h igh by te mov ed t o t blh. operation [m] pr ogram c ode (low by te) tblh pr ogram c ode (high by te) affected f ag(s) none xor a,[m] logical x or d ata m emory to a cc description data i n t he a ccumulator a nd t he s pecifed d ata m emory p erform a b itwise l ogical x or operation. t he re sult is s tored in t he a ccumulator. operation acc a cc x or [ m] affected f ag(s) z xorm a,[m] logical x or a cc to d ata m emory description data i n t he s pecifed d ata m emory a nd t he a ccumulator p erform a b itwise l ogical x or operation. t he re sult is s tored in t he d ata m emory. operation [m] a cc xor [ m] affected f ag(s) z xor a,x logical x or im mediate data to a cc description data i n t he a ccumulator a nd t he s pecifed im mediate data p erform a b itwise l ogical x or operation. t he re sult is s tored in t he a ccumulator. operation acc a cc x or x affected f ag(s) z rev. 1.10 180 de?e??e? 1?? ?01? rev. 1.10 181 de ? e ?? e ? 1 ?? ? 01 ? HT45F75 body fat scale flash mcu HT45F75 body fat scale flash mcu extended instruction defnition the extended instructions are used to directly access the data stored in any data memory sections. ladc a,[m] add d ata m emory to a cc w ith carry description the c ontents o f t he s pecifed d ata m emory, a ccumulator a nd t he c arry f ag a re a dded. the re sult is s tored in t he a ccumulator. operation acc a cc + [ m] + c affected f ag(s) ov, z , a c, c , s c ladcm a,[m] add a cc to d ata m emory w ith carry description the c ontents o f t he s pecifed d ata m emory, a ccumulator a nd t he c arry f ag a re a dded. the re sult is s tored in t he sp ecifed d ata m emory. operation [m] a cc + [ m] + c affected f ag(s) ov, z , a c, c , s c ladd a,[m] add d ata m emory t o a cc description the c ontents o f t he s pecifed d ata m emory a nd t he a ccumulator a re a dded. the re sult is s tored in t he a ccumulator. operation acc a cc + [ m] affected f ag(s) ov, z , a c, c , s c laddm a,[m] add a cc to d ata m emory description the c ontents o f t he s pecifed d ata m emory a nd t he a ccumulator a re a dded. the re sult is s tored in t he sp ecifed d ata m emory. operation [m] a cc + [ m] affected f ag(s) ov, z , a c, c , s c land a,[m] logical a nd d ata m emory t o a cc description data i n t he a ccumulator a nd t he s pecifed d ata m emory p erform a b itwise l ogical a nd operation. t he re sult is s tored in t he a ccumulator. operation acc a cc a nd [ m] affected f ag(s) z landm a,[m] logical a nd a cc to d ata m emory description data i n t he s pecifed d ata m emory a nd t he a ccumulator p erform a b itwise l ogical a nd operation. t he re sult is s tored in t he d ata m emory. operation [m] a cc and [ m] affected f ag(s) z lclr [m] clear d ata m emory description each b it o f t he s pecifed d ata m emory i s cl eared t o 0 . operation [m] 00h affected f ag(s) none lclr [m].i clear bi t o f d ata m emory description bit i o f t he s pecifed d ata m emory i s cl eared t o 0 . operation [m].i 0 affected f ag(s) none rev. 1.10 18 ? de ? e ?? e ? 1 ?? ? 01 ? rev. 1.10 183 de?e??e? 1?? ?01? HT45F75 body fat scale flash mcu HT45F75 body fat scale flash mcu lcpl [m] complement d ata m emory description each b it of t he s pecifed d ata m emory i s l ogically complemented ( 1s complement). b its w hich previously c ontained a 1 a re c hanged to 0 a nd v ice v ersa. operation [m] [m] affected f ag(s) z lcpla [m] complement d ata m emory w ith r esult i n a cc description each b it of t he s pecifed d ata m emory i s l ogically complemented ( 1s complement). b its w hich previously c ontained a 1 a re c hanged to 0 a nd v ice v ersa. th e c omplemented r esult i s s tored i n the a ccumulator a nd t he c ontents o f t he d ata m emory r emain u nchanged. operation acc [ m] affected f ag(s) z ldaa [m] decimal-adjust a cc f or addition w ith r esult i n d ata m emory description convert t he c ontents o f t he a ccumulator v alue to a b cd ( binary c oded d ecimal) v alue resulting f rom t he p revious a ddition o f t wo b cd v ariables. i f t he low n ibble is greater t han 9 or i f a c f ag i s s et, t hen a v alue o f 6 w ill b e a dded to t he l ow n ibble. o therwise t he l ow n ibble remains u nchanged. i f t he h igh n ibble i s g reater t han 9 o r i f t he c f ag i s s et, t hen a v alue o f 6 will b e a dded to t he h igh n ibble. e ssentially, t he decimal c onversion i s p erformed b y a dding 00h, 0 6h, 6 0h o r 6 6h depending o n t he a ccumulator a nd f ag c onditions. o nly t he c f ag may b e a ffected b y t his instruction w hich indicates t hat if t he o riginal b cd s um is greater t han 100, it al lows m ultiple p recision decimal a ddition. operation [m] a cc + 00h or [m] a cc + 06 h o r [m] a cc + 60h o r [m] a cc + 66h affected f ag(s) c ldec [m] decrement d ata m emory description data i n t he s pecifed d ata m emory i s d ecremented b y 1 . operation [m] [ m] ? 1 affected f ag(s) z ldeca [m] decrement d ata m emory wi th r esult i n a cc description data in t he sp ecifed d ata m emory is d ecremented b y 1 . t he re sult is s tored in t he accumulator. th e c ontents o f t he d ata m emory r emain u nchanged. operation acc [ m] ? 1 affected f ag(s) z linc [m] increment d ata m emory description data in t he sp ecifed d ata m emory is incremented b y 1 . operation [m] [ m] + 1 affected f ag(s) z linca [m] increment d ata m emory wi th r esult i n a cc description data i n t he sp ecifed d ata m emory i s i ncremented b y 1 . th e re sult i s s tored i n t he a ccumulator. the c ontents o f t he d ata m emory r emain u nchanged. operation acc [ m] + 1 affected f ag(s) z rev. 1.10 18? de?e??e? 1?? ?01? rev. 1.10 183 de ? e ?? e ? 1 ?? ? 01 ? HT45F75 body fat scale flash mcu HT45F75 body fat scale flash mcu lmov a,[m] move d ata m emory t o a cc description the c ontents o f t he s pecifed d ata m emory a re c opied to t he a ccumulator. operation acc [ m] affected f ag(s) none lmov [m],a move a cc to d ata m emory description the c ontents o f t he a ccumulator a re c opied to t he s pecifed d ata m emory. operation [m] a cc affected f ag(s) none lor a,[m] logical o r d ata m emory to a cc description data i n t he a ccumulator a nd t he s pecifed d ata m emory p erform a b itwise logical o r op eration. t he re sult is s tored in t he a ccumulator. operation acc a cc or [ m] affected f ag(s) z lorm a,[m] logical or a cc to d ata m emory description data i n t he s pecifed d ata m emory a nd t he a ccumulator p erform a b itwise l ogical o r operation. t he re sult is s tored in t he d ata m emory. operation [m] a cc or [ m] affected f ag(s) z lrl [m] rotate d ata m emory l eft description the c ontents o f t he s pecifed d ata m emory a re r otated l eft b y 1 b it w ith b it 7 r otated i nto b it 0 . operation [m].(i+1) [ m].i; (i=0~6) [m].0 [ m].7 affected f ag(s) none lrla [m] rotate d ata m emory left w ith re sult in a cc description the c ontents o f t he s pecifed d ata m emory a re r otated l eft b y 1 b it w ith b it 7 r otated i nto b it 0 . the r otated r esult i s s tored i n t he a ccumulator a nd t he c ontents o f t he d ata m emory r emain u nchanged. operation acc.(i+1) [ m].i; (i=0~6) acc.0 [ m].7 affected f ag(s) none lrlc [m] rotate d ata m emory l eft t hrough carry description the c ontents o f t he s pecifed d ata m emory a nd t he c arry f ag a re r otated l eft b y 1 b it. b it 7 replaces t he c arry b it a nd t he o riginal c arry f ag i s r otated i nto b it 0 . operation [m].(i+1) [ m].i; (i=0~6) [m].0 c c [ m].7 affected f ag(s) c lrlca [m] rotate d ata m emory left t hrough c arry w ith re sult in a cc description data i n t he s pecifed d ata m emory and t he carry f ag are r otated l eft b y 1 b it. b it 7 r eplaces t he carry b it a nd t he o riginal c arry f ag i s r otated i nto t he b it 0 . th e r otated r esult i s s tored i n t he accumulator a nd t he c ontents o f t he d ata m emory r emain u nchanged. operation acc.(i+1) [ m].i; (i=0~6) acc.0 c c [ m].7 affected f ag(s) c rev. 1.10 18 ? de ? e ?? e ? 1 ?? ? 01 ? rev. 1.10 185 de?e??e? 1?? ?01? HT45F75 body fat scale flash mcu HT45F75 body fat scale flash mcu lrr [m] rotate d ata m emory r ight description the contents of t he s pecifed d ata m emory are r otated r ight b y 1 b it w ith b it 0 r otated i nto b it 7 . operation [m].i [ m].(i+1); (i=0~6) [m].7 [ m].0 affected f ag(s) none lrra [m] rotate d ata m emory right with result i n a cc description data i n t he s pecifed d ata m emory a nd t he c arry f ag a re r otated r ight b y 1 b it w ith b it 0 rotated i nto b it 7 . th e r otated r esult i s s tored i n t he a ccumulator a nd t he c ontents o f t he data m emory r emain u nchanged. operation acc.i [ m].(i+1); (i=0~6) acc.7 [ m].0 affected f ag(s) none lrrc [m] rotate d ata m emory r ight t hrough carry description the c ontents o f t he s pecifed d ata m emory a nd t he c arry f ag a re r otated r ight b y 1 b it. b it 0 replaces t he c arry b it a nd t he o riginal c arry f ag i s r otated i nto b it 7 . operation [m].i [ m].(i+1); (i=0~6) [m].7 c c [ m].0 affected f ag(s) c lrrca [m] rotate d ata m emory right th rough c arry with result i n a cc description data i n t he s pecifed d ata m emory a nd t he c arry f ag a re r otated r ight b y 1 b it. b it 0 r eplaces the c arry b it a nd t he o riginal c arry f ag i s r otated i nto b it 7 . th e r otated r esult i s s tored i n t he accumulator a nd t he c ontents o f t he d ata m emory r emain u nchanged. operation acc.i [ m].(i+1); (i=0~6) acc.7 c c [ m].0 affected f ag(s) c lsbc a,[m] subtract d ata m emory from a cc wi th c arry description the c ontents o f t he s pecifed d ata m emory a nd t he c omplement o f t he c arry f ag a re subtracted f rom t he a ccumulator. t he re sult is s tored in t he a ccumulator. n ote t hat if t he result o f s ubtraction is n egative, t he c f ag w ill b e c leared t o 0 , o therwise if t he re sult is positive o r z ero, t he c f ag w ill b e s et to 1 . operation acc a cc ? [ m] ? c affected f ag(s) ov, z , a c, c , s c, c z lsbcm a,[m] subtract d ata m emory from a cc wi th c arry a nd r esult i n d ata m emory description the c ontents o f t he s pecifed d ata m emory a nd t he c omplement o f t he c arry f ag a re subtracted f rom t he a ccumulator. t he re sult is s tored in t he d ata m emory. n ote t hat if t he result o f s ubtraction is n egative, t he c f ag w ill b e c leared t o 0 , o therwise if t he re sult is positive o r z ero, t he c f ag w ill b e s et to 1 . operation [m] a cc ? [ m] ? c affected f ag(s) ov, z , a c, c , s c, c z rev. 1.10 18? de?e??e? 1?? ?01? rev. 1.10 185 de ? e ?? e ? 1 ?? ? 01 ? HT45F75 body fat scale flash mcu HT45F75 body fat scale flash mcu lsdz [m] skip i f decrement d ata m emory i s 0 description the c ontents o f t he s pecifed d ata m emory a re fr st decremented b y 1 . i f t he r esult i s 0 t he following instruction is s kipped. a s t his re quires t he insertion o f a d ummy instruction w hile the n ext instruction is f etched, it is a t wo c ycle instruction. i f t he re sult is n ot 0 t he p rogram proceeds w ith t he f ollowing i nstruction. operation [m] [ m] ? 1 skip if [ m]=0 affected f ag(s) none lsdza [m] skip i f decrement d ata m emory i s z ero w ith r esult i n a cc description the c ontents o f t he s pecifed d ata m emory a re fr st decremented b y 1 . i f t he r esult i s 0 , t he following instruction is s kipped. t he re sult is s tored in t he a ccumulator b ut t he sp ecifed data m emory c ontents r emain u nchanged. a s t his r equires t he i nsertion o f a dummy instruction w hile t he n ext instruction is f etched, it is a t wo c ycle instruction. i f t he r esult is n ot 0 , the p rogram p roceeds w ith t he f ollowing instruction. operation acc [ m] ? 1 skip if a cc=0 affected f ag(s) none lset [m] set d ata m emory description each b it o f t he s pecifed d ata m emory i s s et t o 1 . operation [m] f fh affected f ag(s) none lset [m].i set b it o f d ata m emory description bit i o f t he s pecifed d ata m emory i s s et t o 1 . operation [m].i 1 affected f ag(s) none lsiz [m] skip i f i ncrement d ata m emory i s 0 description the c ontents o f t he sp ecifed d ata m emory a re f rst incremented b y 1 . i f t he re sult is 0 , t he following instruction is s kipped. a s t his re quires t he insertion o f a d ummy instruction w hile the n ext instruction is f etched, it is a t wo c ycle instruction. i f t he re sult is n ot 0 t he p rogram proceeds w ith t he f ollowing i nstruction. operation [m] [ m] + 1 skip if [ m]=0 affected f ag(s) none lsiza [m] skip if increment d ata m emory is z ero w ith re sult in a cc description the c ontents o f t he sp ecifed d ata m emory a re f rst incremented b y 1 . i f t he re sult is 0 , t he following instruction is s kipped. t he re sult is s tored in t he a ccumulator b ut t he sp ecifed data m emory c ontents r emain u nchanged. a s t his r equires t he i nsertion o f a dummy instruction w hile t he n ext instruction is f etched, it is a t wo c ycle instruction. i f t he re sult is n ot 0 t he p rogram p roceeds w ith t he f ollowing instruction. operation acc [ m] + 1 skip if a cc=0 affected f ag(s) none lsnz [m].i skip i f d ata m emory i s no t 0 description if t he sp ecifed d ata m emory is n ot 0 , t he f ollowing instruction is s kipped. a s t his re quires t he insertion o f a d ummy instruction w hile t he n ext instruction is f etched, it is a t wo c ycle instruction. i f t he re sult is 0 t he p rogram p roceeds w ith t he f ollowing instruction. operation skip i f [ m].i 0 affected f ag(s) none rev. 1.10 18 ? de ? e ?? e ? 1 ?? ? 01 ? rev. 1.10 187 de?e??e? 1?? ?01? HT45F75 body fat scale flash mcu HT45F75 body fat scale flash mcu lsnz [m] skip i f d ata m emory i s no t 0 description if t he c ontent o f t he sp ecifed d ata m emory is n ot 0 , t he f ollowing instruction is s kipped. a s this re quires t he insertion o f a d ummy instruction w hile t he n ext instruction is f etched, it is a two c ycle instruction. i f t he re sult is 0 t he p rogram p roceeds w ith t he f ollowing instruction. operation skip i f [ m] 0 affected f ag(s) none lsub a,[m] subtract d ata m emory from a cc description the s pecifed d ata m emory i s s ubtracted f rom t he c ontents o f t he a ccumulator. th e r esult i s stored in t he a ccumulator. n ote t hat if t he re sult o f s ubtraction is n egative, t he c f ag w ill b e cleared to 0 , o therwise i f t he r esult i s p ositive o r z ero, t he c f ag w ill b e s et to 1 . operation acc a cc ? [ m] affected f ag(s) ov, z , a c, c , s c, c z lsubm a,[m] subtract d ata m emory from a cc wi th r esult i n d ata m emory description the s pecifed d ata m emory i s s ubtracted f rom t he c ontents o f t he a ccumulator. th e r esult i s stored in t he d ata m emory. n ote t hat if t he re sult o f s ubtraction is n egative, t he c f ag w ill b e cleared to 0 , o therwise i f t he r esult i s p ositive o r z ero, t he c f ag w ill b e s et to 1 . operation [m] a cc ? [ m] affected f ag(s) ov, z , a c, c , s c, c z lswap [m] swap ni bbles of d ata m emory description the l ow-order a nd h igh-order n ibbles o f t he s pecifed d ata m emory a re i nterchanged. operation [m].3~[m].0 ? [ m].7~[m].4 affected f ag(s) none lswapa [m] swap ni bbles of d ata m emory w ith r esult i n a cc description the l ow-order a nd h igh-order n ibbles o f t he s pecifed d ata m emory a re i nterchanged. th e result i s s tored i n t he a ccumulator. th e c ontents o f t he d ata m emory r emain u nchanged. operation acc.3~acc.0 [ m].7~[m].4 acc.7~acc.4 [ m].3~[m].0 affected f ag(s) none lsz [m] skip i f d ata m emory i s 0 description if t he contents of t he s pecifed d ata m emory i s 0, t he following i nstruction i s s kipped. a s t his requires t he insertion o f a d ummy instruction w hile t he n ext instruction is f etched, it is a t wo cycle instruction. i f t he re sult is n ot 0 t he p rogram p roceeds w ith t he f ollowing instruction. operation skip if [ m]=0 affected f ag(s) none lsza [m] skip i f d ata m emory i s 0 w ith data m ovement to a cc description the c ontents o f t he s pecifed d ata m emory a re c opied to t he a ccumulator. i f t he v alue i s z ero, the f ollowing instruction is s kipped. a s t his re quires t he insertion o f a d ummy instruction while t he n ext instruction is f etched, it is a t wo c ycle instruction. i f t he re sult is n ot 0 t he program p roceeds w ith t he f ollowing instruction. operation acc [ m] skip if [ m]=0 affected f ag(s) none rev. 1.10 18? de?e??e? 1?? ?01? rev. 1.10 187 de ? e ?? e ? 1 ?? ? 01 ? HT45F75 body fat scale flash mcu HT45F75 body fat scale flash mcu lsz [m].i skip i f b it i of d ata m emory i s 0 description if b it i o f t he sp ecifed d ata m emory is 0 , t he f ollowing instruction is s kipped. a s t his re quires the insertion o f a d ummy instruction w hile t he n ext instruction is f etched, it is a t wo c ycle instruction. i f t he re sult is n ot 0 , t he p rogram p roceeds w ith t he f ollowing instruction. operation skip if [ m].i=0 affected f ag(s) none ltabrd [m] read ta ble ( current p age) to t blh a nd d ata m emory description the low b yte o f t he p rogram c ode ( current p age) a ddressed b y t he t able p ointer ( tblp) is moved t o t he s pecifed d ata m emory a nd t he h igh by te mo ved t o t blh. operation [m] pr ogram c ode (low by te) tblh pr ogram c ode (high by te) affected f ag(s) none ltabrdl [m] read t able (last p age) t o t blh a nd d ata m emory description the l ow by te o f t he pr ogram c ode (last p age) a ddressed by t he t able p ointer (tblp) i s mo ved to t he s pecifed d ata m emory a nd t he h igh b yte m oved to t blh. operation [m] pr ogram c ode (low by te) tblh pr ogram c ode (high by te) affected f ag(s) none litabrd [m] increment ta ble p ointer l ow b yte fr st and r ead ta ble to t blh and d ata m emory description increment ta ble p ointer l ow b yte, t blp, fr st and t hen t he p rogram code addressed b y t he table p ointer ( tbhp and t blp) i s m oved to t he s pecifed d ata m emory and t he hi gh b yte moved t o t blh. operation [m] pr ogram c ode (low by te) tblh pr ogram c ode (high by te) affected f ag(s) none litabrdl [m] increment t able p ointer l ow by te f rst a nd r ead t able (last p age) t o t blh a nd d ata m emory description increment ta ble p ointer l ow b yte, t blp, fr st and t hen t he l ow b yte of t he p rogram code (last p age) addressed b y t he ta ble p ointer ( tblp) i s m oved to t he s pecifed d ata m emory and the h igh by te mov ed t o t blh. operation [m] pr ogram c ode (low by te) tblh pr ogram c ode (high by te) affected f ag(s) none lxor a,[m] logical x or d ata m emory to a cc description data i n t he a ccumulator a nd t he s pecifed d ata m emory p erform a b itwise l ogical x or operation. t he re sult is s tored in t he a ccumulator. operation acc a cc x or [ m] affected f ag(s) z lxorm a,[m] logical x or a cc to d ata m emory description data i n t he s pecifed d ata m emory a nd t he a ccumulator p erform a b itwise l ogical x or operation. t he re sult is s tored in t he d ata m emory. operation [m] a cc xor [ m] affected f ag(s) z rev. 1.10 188 de ? e ?? e ? 1 ?? ? 01 ? rev. 1.10 189 de?e??e? 1?? ?01? HT45F75 body fat scale flash mcu HT45F75 body fat scale flash mcu package information note that the package information provided here is for consultation purposes only . as this information may be updated at regular intervals users are reminded to consult the holtek website for the latest version of the package/carton information . additional supplementary information with regard to pa ckaging is listed below. click on the relevant section to be transferred to the relevant website page. ? further package information (include outline dimensions, product t ape and reel specifcations) ? packing meterials information ? carton information rev. 1.10 188 de?e??e? 1?? ?01? rev. 1.10 189 de ? e ?? e ? 1 ?? ? 01 ? HT45F75 body fat scale flash mcu HT45F75 body fat scale flash mcu 48-pin lqfp (7mm7mm) outline dimensions symbol dimensions in inch min. nom. max. a 0.35 ? bsc b 0. ? 7 ? bsc c 0.35 ? bsc d 0. ? 7 ? bsc e 0.0 ? 0 bsc f 0.007 0.009 0.011 g 0.053 0.055 0.057 h 0.0 ? 3 i 0.00 ? 0.00 ? j 0.018 0.0 ?? 0.030 k 0.00 ? 0.008 0 7 symbol dimensions in mm min. nom. max. a 9.00 bsc b 7.00 bsc c 9.00 bsc d 7.00 bsc e 0.50 bsc f 0.17 0. ?? 0. ? 7 g 1.35 1. ? 0 1. ? 5 h 1. ? 0 i 0.05 0.15 j 0. ? 5 0. ? 0 0.75 k 0.09 0. ? 0 0 7 rev. 1.10 190 de ? e ?? e ? 1 ?? ? 01 ? rev. 1.10 pb de?e??e? 1?? ?01? HT45F75 body fat scale flash mcu HT45F75 body fat scale flash mcu copy ? ight ? ? 01 ? ? y holtek semiconductor inc. the info ?? ation appea ? ing in this data sheet is ? elieved to ? e a ?? u ? ate at the ti ? e of pu ? li ? ation. howeve ?? holtek assu ? es no ? esponsi ? ility a ? ising f ? o ? the use of the specifcations described. the applications mentioned herein are used solely fo ? the pu ? pose of illust ? ation and holtek ? akes no wa ?? anty o ? ? ep ? esentation that su ? h appli ? ations will ? e suita ? le without fu ? the ? ? odifi ? ation ? no ? ? e ? o ?? ends the use of its p ? odu ? ts fo ? appli ? ation that ? ay p ? esent a ? isk to hu ? an life due to ? alfun ? tion o ? othe ? wise. holtek's p ? odu ? ts a ? e not autho ? ized fo ? use as ?? iti ? al ? o ? ponents in life suppo ? t devi ? es o ? syste ? s. holtek ? ese ? ves the ? ight to alte ? its products without prior notifcation. for the most up-to-date information, please visit ou ? we ? site at http://www.holtek. ? o ? .tw. |
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